diff options
author | Ley Foon Tan <ley.foon.tan@intel.com> | 2019-11-08 10:38:20 +0800 |
---|---|---|
committer | Marek Vasut <marex@denx.de> | 2020-01-07 14:38:33 +0100 |
commit | db5741f7a85ec3ee79b64496172afaa7dc2cb225 (patch) | |
tree | 20f749d41ff3c329758f16c1a67f9c5772f35278 /arch/arm/mach-socfpga/reset_manager_s10.c | |
parent | bb25aca1343304e0334e9eebfb9d350eaf276882 (diff) |
arm: socfpga: Convert system manager from struct to defines
Convert system manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.
Change to get system manager base address from DT node instead of
using #define.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Diffstat (limited to 'arch/arm/mach-socfpga/reset_manager_s10.c')
-rw-r--r-- | arch/arm/mach-socfpga/reset_manager_s10.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index 8af28ee410..e92de3d84e 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -12,9 +12,6 @@ DECLARE_GLOBAL_DATA_PTR; -static const struct socfpga_system_manager *system_manager_base = - (void *)SOCFPGA_SYSMGR_ADDRESS; - /* Assert or de-assert SoCFPGA reset manager reset. */ void socfpga_per_reset(u32 reset, int set) { @@ -59,29 +56,32 @@ void socfpga_bridges_reset(int enable) { if (enable) { /* clear idle request to all bridges */ - setbits_le32(&system_manager_base->noc_idlereq_clr, ~0); + setbits_le32(socfpga_get_sysmgr_addr() + + SYSMGR_S10_NOC_IDLEREQ_CLR, ~0); /* Release all bridges from reset state */ clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_S10_BRGMODRST, ~0); /* Poll until all idleack to 0 */ - while (readl(&system_manager_base->noc_idleack)) + while (readl(socfpga_get_sysmgr_addr() + + SYSMGR_S10_NOC_IDLEACK)) ; } else { /* set idle request to all bridges */ - writel(~0, &system_manager_base->noc_idlereq_set); + writel(~0, + socfpga_get_sysmgr_addr() + SYSMGR_S10_NOC_IDLEREQ_SET); /* Enable the NOC timeout */ - writel(1, &system_manager_base->noc_timeout); + writel(1, socfpga_get_sysmgr_addr() + SYSMGR_S10_NOC_TIMEOUT); /* Poll until all idleack to 1 */ - while ((readl(&system_manager_base->noc_idleack) ^ + while ((readl(socfpga_get_sysmgr_addr() + SYSMGR_S10_NOC_IDLEACK) ^ (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK))) ; /* Poll until all idlestatus to 1 */ - while ((readl(&system_manager_base->noc_idlestatus) ^ + while ((readl(socfpga_get_sysmgr_addr() + SYSMGR_S10_NOC_IDLESTATUS) ^ (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK))) ; @@ -91,7 +91,7 @@ void socfpga_bridges_reset(int enable) RSTMGR_BRGMODRST_FPGA2SOC_MASK)); /* Disable NOC timeout */ - writel(0, &system_manager_base->noc_timeout); + writel(0, socfpga_get_sysmgr_addr() + SYSMGR_S10_NOC_TIMEOUT); } } |