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authorDalon Westergreen <dwesterg@gmail.com>2017-04-18 08:11:16 -0700
committerMarek Vasut <marek.vasut+renesas@gmail.com>2017-04-25 12:46:44 +0200
commit6bd041f00d5d80761852eae1ecb7879a27f3c289 (patch)
tree69ddce8539a156f964f15d6e9e3fcbf81b12f179 /arch/arm/mach-socfpga/Kconfig
parent3c476d841daa491f87c8f07851038afbdf4d90a8 (diff)
arm: socfpga: add cyclone5 based de10-nano board
Add support for the Terasic DE10-Nano board. The board is based on the DE0-Nano-Soc board but adds a larger FPGA and an HDMI output. Signed-off-by: Dalon Westergreen <dwesterg@gmail.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'arch/arm/mach-socfpga/Kconfig')
-rw-r--r--arch/arm/mach-socfpga/Kconfig7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 9bfee04098..f6e5773272 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -82,6 +82,10 @@ config TARGET_SOCFPGA_TERASIC_DE0_NANO
bool "Terasic DE0-Nano-Atlas (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
+config TARGET_SOCFPGA_TERASIC_DE10_NANO
+ bool "Terasic DE10-Nano (Cyclone V)"
+ select TARGET_SOCFPGA_CYCLONE5
+
config TARGET_SOCFPGA_TERASIC_DE1_SOC
bool "Terasic DE1-SoC (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
@@ -97,6 +101,7 @@ config SYS_BOARD
default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
+ default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
default "is1" if TARGET_SOCFPGA_IS1
default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
@@ -112,6 +117,7 @@ config SYS_VENDOR
default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
+ default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
config SYS_SOC
@@ -122,6 +128,7 @@ config SYS_CONFIG_NAME
default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
+ default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
default "socfpga_is1" if TARGET_SOCFPGA_IS1
default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT