diff options
| author | Holger Brunck <holger.brunck@ch.abb.com> | 2020-02-19 19:55:14 +0100 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2020-03-03 22:11:36 +0100 |
| commit | 468ba8d00b5af7828302e297736ae23d4873cfb0 (patch) | |
| tree | 1a60a77e307bbd56fb4733807d3c8a2586f80508 /arch/arm/mach-socfpga/Kconfig | |
| parent | 85f748ad953e92e62831bff24bfd2260ef23325c (diff) | |
ARM: socfpga: Add initial support for the ABB SECU board
Add initial support for the ABB SECU board, which is an ArriaV-based
SoCFPGA system with ethernet and booting from Denali NAND.
Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Diffstat (limited to 'arch/arm/mach-socfpga/Kconfig')
| -rw-r--r-- | arch/arm/mach-socfpga/Kconfig | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 969698c83f..38d6c1b2ba 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -96,6 +96,11 @@ config TARGET_SOCFPGA_ARRIA10_SOCDK bool "Altera SOCFPGA SoCDK (Arria 10)" select TARGET_SOCFPGA_ARRIA10 +config TARGET_SOCFPGA_ARRIA5_SECU1 + bool "ABB SECU1 (Arria V)" + select TARGET_SOCFPGA_ARRIA5 + select VENDOR_KM + config TARGET_SOCFPGA_ARRIA5_SOCDK bool "Altera SOCFPGA SoCDK (Arria V)" select TARGET_SOCFPGA_ARRIA5 @@ -158,6 +163,7 @@ config SYS_BOARD default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO default "is1" if TARGET_SOCFPGA_IS1 default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK + default "secu1" if TARGET_SOCFPGA_ARRIA5_SECU1 default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "sr1500" if TARGET_SOCFPGA_SR1500 @@ -173,6 +179,7 @@ config SYS_VENDOR default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES + default "keymile" if TARGET_SOCFPGA_ARRIA5_SECU1 default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC @@ -184,6 +191,7 @@ config SYS_SOC config SYS_CONFIG_NAME default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK + default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1 default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK @@ -199,4 +207,6 @@ config SYS_CONFIG_NAME default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA +source "board/keymile/Kconfig" + endif |