diff options
| author | Kever Yang <kever.yang@rock-chips.com> | 2017-11-30 16:51:19 +0800 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2017-11-30 22:55:27 +0100 |
| commit | faa75ad9e6de20776e4629a2eb71c372b9fcfa7d (patch) | |
| tree | 049a59419c5b3071168505cb745ce228290e655b /arch/arm/mach-rockchip | |
| parent | f9cf8cbb9e23952c5585ab3a548af3599a925578 (diff) | |
rockchip: rk3036: fix pll config for correct frequency
There is a fixed div-2 between PLL and clk_ddr/clk_ddrphy,
so we need to double to pll output and then ddr can work
in correct frequency.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Diffstat (limited to 'arch/arm/mach-rockchip')
| -rw-r--r-- | arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c index 460dd6074e..1d3fc1a622 100644 --- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c @@ -34,10 +34,11 @@ struct rk3036_sdram_priv { struct rk3036_ddr_config ddr_config; }; -/* use integer mode, 396MHz dpll setting +/* + * use integer mode, dpll output 792MHz and ddr get 396MHz * refdiv, fbdiv, postdiv1, postdiv2 */ -const struct pll_div dpll_init_cfg = {1, 50, 3, 1}; +const struct pll_div dpll_init_cfg = {1, 66, 2, 1}; /* 396Mhz ddr timing */ const struct rk3036_ddr_timing ddr_timing = {0x18c, |