rockchip: rk3128: add soc basic support

RK3128 is a SoC from Rockchip with quad-core Cortex-A7 CPU
and mali400 GPU. Support Nand flash, eMMC, SD card, USB 2.0 host
and device, HDMI/LVDS/MIPI display.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

7 files changed, 180 insertions, 0 deletions

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index a26736a5ac..1e74db3607 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -11,6 +11,15 @@ config ROCKCHIP_RK3036
 	  and video codec support. Peripherals include Gigabit Ethernet,
 	  USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
 
+config ROCKCHIP_RK3128
+	bool "Support Rockchip RK3128"
+	select CPU_V7
+	help
+	  The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
+	  including NEON and GPU, Mali-400 graphics, several DDR3 options
+	  and video codec support. Peripherals include Gigabit Ethernet,
+	  USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
+
 config ROCKCHIP_RK3188
 	bool "Support Rockchip RK3188"
 	select CPU_V7
@@ -211,6 +220,7 @@ config SPL_MMC_SUPPORT
 	default y if !SPL_ROCKCHIP_BACK_TO_BROM
 
 source "arch/arm/mach-rockchip/rk3036/Kconfig"
+source "arch/arm/mach-rockchip/rk3128/Kconfig"
 source "arch/arm/mach-rockchip/rk3188/Kconfig"
 source "arch/arm/mach-rockchip/rk322x/Kconfig"
 source "arch/arm/mach-rockchip/rk3288/Kconfig"
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 7e1f864383..e1b0519b1f 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -30,6 +30,7 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
 obj-y += boot_mode.o
 
 obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o
+obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128-board.o
 obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o
 obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o
 obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o
@@ -43,6 +44,7 @@ obj-y += rk_timer.o
 endif
 
 obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
+obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/
 ifndef CONFIG_TPL_BUILD
 obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/
 endif
diff --git a/arch/arm/mach-rockchip/rk3128-board.c b/arch/arm/mach-rockchip/rk3128-board.c
new file mode 100644
index 0000000000..2e8393d70a
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3128-board.c
@@ -0,0 +1,127 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <ram.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/grf_rk3128.h>
+#include <asm/arch/boot_mode.h>
+#include <asm/arch/timer.h>
+#include <power/regulator.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+__weak int rk_board_late_init(void)
+{
+	return 0;
+}
+
+int board_late_init(void)
+{
+	setup_boot_mode();
+
+	return rk_board_late_init();
+}
+
+int board_init(void)
+{
+	int ret = 0;
+
+	rockchip_timer_init();
+
+	ret = regulators_enable_boot_on(false);
+	if (ret) {
+		debug("%s: Cannot enable boot on regulator\n", __func__);
+		return ret;
+	}
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = 0x8400000;
+	/* Reserve 0xe00000(14MB) for OPTEE with TA enabled, otherwise 2MB */
+	gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
+				+ gd->bd->bi_dram[0].size + 0xe00000;
+	gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
+				+ gd->ram_size - gd->bd->bi_dram[1].start;
+
+	return 0;
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+#endif
+
+#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
+#include <usb.h>
+#include <usb/dwc2_udc.h>
+
+static struct dwc2_plat_otg_data rk3128_otg_data = {
+	.rx_fifo_sz	= 512,
+	.np_tx_fifo_sz	= 16,
+	.tx_fifo_sz	= 128,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	int node;
+	const char *mode;
+	bool matched = false;
+	const void *blob = gd->fdt_blob;
+
+	/* find the usb_otg node */
+	node = fdt_node_offset_by_compatible(blob, -1,
+					     "rockchip,rk3128-usb");
+
+	while (node > 0) {
+		mode = fdt_getprop(blob, node, "dr_mode", NULL);
+		if (mode && strcmp(mode, "otg") == 0) {
+			matched = true;
+			break;
+		}
+
+		node = fdt_node_offset_by_compatible(blob, node,
+						     "rockchip,rk3128-usb");
+	}
+	if (!matched) {
+		debug("Not found usb_otg device\n");
+		return -ENODEV;
+	}
+	rk3128_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
+
+	return dwc2_udc_probe(&rk3128_otg_data);
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_USB_FUNCTION_FASTBOOT)
+int fb_set_reboot_flag(void)
+{
+	struct rk3128_grf *grf;
+
+	printf("Setting reboot to fastboot flag ...\n");
+	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	/* Set boot mode to fastboot */
+	writel(BOOT_FASTBOOT, &grf->os_reg[0]);
+
+	return 0;
+}
+#endif
diff --git a/arch/arm/mach-rockchip/rk3128/Kconfig b/arch/arm/mach-rockchip/rk3128/Kconfig
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3128/Kconfig
diff --git a/arch/arm/mach-rockchip/rk3128/Makefile b/arch/arm/mach-rockchip/rk3128/Makefile
new file mode 100644
index 0000000000..0f63d921de
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3128/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2017 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y += rk3128.o
+obj-y += syscon_rk3128.o
diff --git a/arch/arm/mach-rockchip/rk3128/rk3128.c b/arch/arm/mach-rockchip/rk3128/rk3128.c
new file mode 100644
index 0000000000..9d6e3b1ee1
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3128/rk3128.c
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+int arch_cpu_init(void)
+{
+	/* We do some SoC one time setting here. */
+
+	return 0;
+}
diff --git a/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c b/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c
new file mode 100644
index 0000000000..0b636390ac
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c
@@ -0,0 +1,21 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+
+static const struct udevice_id rk3128_syscon_ids[] = {
+	{ .compatible = "rockchip,rk3128-grf", .data = ROCKCHIP_SYSCON_GRF },
+	{ }
+};
+
+U_BOOT_DRIVER(syscon_rk3128) = {
+	.name = "rk3128_syscon",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3128_syscon_ids,
+};