diff options
author | Joseph Chen <chenjh@rock-chips.com> | 2021-06-02 15:58:25 +0800 |
---|---|---|
committer | Kever Yang <kever.yang@rock-chips.com> | 2021-06-18 14:36:24 +0800 |
commit | 2a950e3ba5063a6c23bdcde2d5224ffb9abb5a93 (patch) | |
tree | b4002647ce28ff8b227568125dc69b913fc00d2c /arch/arm/mach-rockchip | |
parent | 2d46775287e3e421e5c1369ddc04626ccf52c23d (diff) |
rockchip: Add rk3568 architecture core
RK3568 is a high-performance and low power quad-core application
processor designed for personal mobile internet device and AIoT
equipments.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'arch/arm/mach-rockchip')
-rw-r--r-- | arch/arm/mach-rockchip/Kconfig | 17 | ||||
-rw-r--r-- | arch/arm/mach-rockchip/Makefile | 1 | ||||
-rw-r--r-- | arch/arm/mach-rockchip/rk3568/Kconfig | 20 | ||||
-rw-r--r-- | arch/arm/mach-rockchip/rk3568/Makefile | 9 | ||||
-rw-r--r-- | arch/arm/mach-rockchip/rk3568/clk_rk3568.c | 53 | ||||
-rw-r--r-- | arch/arm/mach-rockchip/rk3568/rk3568.c | 85 | ||||
-rw-r--r-- | arch/arm/mach-rockchip/rk3568/syscon_rk3568.c | 24 |
7 files changed, 209 insertions, 0 deletions
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 407bf3fbeae..4a2d35aee22 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -257,6 +257,23 @@ config ROCKCHIP_RK3399 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. +config ROCKCHIP_RK3568 + bool "Support Rockchip RK3568" + select ARM64 + select CLK + select PINCTRL + select RAM + select REGMAP + select SYSCON + select BOARD_LATE_INIT + imply ROCKCHIP_COMMON_BOARD + help + The Rockchip RK3568 is a ARM-based SoC with quad-core Cortex-A55, + including NEON and GPU, 512K L3 cache, Mali-G52 based graphics, + two video interfaces supporting HDMI and eDP, several DDR3 options + and video codec support. Peripherals include Gigabit Ethernet, + USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. + config ROCKCHIP_RV1108 bool "Support Rockchip RV1108" select CPU_V7A diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 121f23a563e..00aef0ecee6 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -42,6 +42,7 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += rk3308/ obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/ obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/ obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/ +obj-$(CONFIG_ROCKCHIP_RK3568) += rk3568/ obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/ # Clear out SPL objects, in case this is a TPL build diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig new file mode 100644 index 00000000000..201c63c2a9c --- /dev/null +++ b/arch/arm/mach-rockchip/rk3568/Kconfig @@ -0,0 +1,20 @@ +if ROCKCHIP_RK3568 + +config TARGET_EVB_RK3568 + bool "RK3568 evaluation board" + select BOARD_LATE_INIT + help + RK3568 EVB is a evaluation board for Rockchp RK3568. + +config ROCKCHIP_BOOT_MODE_REG + default 0xfdc20200 + +config SYS_SOC + default "rk3568" + +config SYS_MALLOC_F_LEN + default 0x2000 + +source "board/rockchip/evb_rk3568/Kconfig" + +endif diff --git a/arch/arm/mach-rockchip/rk3568/Makefile b/arch/arm/mach-rockchip/rk3568/Makefile new file mode 100644 index 00000000000..28c1f4ee5c9 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3568/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2021 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += clk_rk3568.o +obj-y += rk3568.o +obj-y += syscon_rk3568.o diff --git a/arch/arm/mach-rockchip/rk3568/clk_rk3568.c b/arch/arm/mach-rockchip/rk3568/clk_rk3568.c new file mode 100644 index 00000000000..8917edcbd30 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3568/clk_rk3568.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2021 Rockchip Electronics Co., Ltd + */ + +#include <common.h> +#include <dm.h> +#include <syscon.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3568.h> +#include <linux/err.h> + +int rockchip_get_clk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(rockchip_rk3568_cru), devp); +} + +void *rockchip_get_cru(void) +{ + struct rk3568_clk_priv *priv; + struct udevice *dev; + int ret; + + ret = rockchip_get_clk(&dev); + if (ret) + return ERR_PTR(ret); + + priv = dev_get_priv(dev); + + return priv->cru; +} + +static int rockchip_get_pmucruclk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(rockchip_rk3568_pmucru), devp); +} + +void *rockchip_get_pmucru(void) +{ + struct rk3568_pmuclk_priv *priv; + struct udevice *dev; + int ret; + + ret = rockchip_get_pmucruclk(&dev); + if (ret) + return ERR_PTR(ret); + + priv = dev_get_priv(dev); + + return priv->pmucru; +} diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c new file mode 100644 index 00000000000..973b4f9dcbd --- /dev/null +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2021 Rockchip Electronics Co., Ltd + */ + +#include <common.h> +#include <dm.h> +#include <asm/armv8/mmu.h> +#include <asm/io.h> +#include <asm/arch-rockchip/grf_rk3568.h> +#include <asm/arch-rockchip/hardware.h> +#include <dt-bindings/clock/rk3568-cru.h> + +#define PMUGRF_BASE 0xfdc20000 +#define GRF_BASE 0xfdc60000 + +/* PMU_GRF_GPIO0D_IOMUX_L */ +enum { + GPIO0D1_SHIFT = 4, + GPIO0D1_MASK = GENMASK(6, 4), + GPIO0D1_GPIO = 0, + GPIO0D1_UART2_TXM0, + + GPIO0D0_SHIFT = 0, + GPIO0D0_MASK = GENMASK(2, 0), + GPIO0D0_GPIO = 0, + GPIO0D0_UART2_RXM0, +}; + +/* GRF_IOFUNC_SEL3 */ +enum { + UART2_IO_SEL_SHIFT = 10, + UART2_IO_SEL_MASK = GENMASK(11, 10), + UART2_IO_SEL_M0 = 0, +}; + +static struct mm_region rk3568_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0xf0000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xf0000000UL, + .phys = 0xf0000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0x300000000, + .phys = 0x300000000, + .size = 0x0c0c00000, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = rk3568_mem_map; + +void board_debug_uart_init(void) +{ + static struct rk3568_pmugrf * const pmugrf = (void *)PMUGRF_BASE; + static struct rk3568_grf * const grf = (void *)GRF_BASE; + + /* UART2 M0 */ + rk_clrsetreg(&grf->iofunc_sel3, UART2_IO_SEL_MASK, + UART2_IO_SEL_M0 << UART2_IO_SEL_SHIFT); + + /* Switch iomux */ + rk_clrsetreg(&pmugrf->pmu_gpio0d_iomux_l, + GPIO0D1_MASK | GPIO0D0_MASK, + GPIO0D1_UART2_TXM0 << GPIO0D1_SHIFT | + GPIO0D0_UART2_RXM0 << GPIO0D0_SHIFT); +} + +int arch_cpu_init(void) +{ + return 0; +} diff --git a/arch/arm/mach-rockchip/rk3568/syscon_rk3568.c b/arch/arm/mach-rockchip/rk3568/syscon_rk3568.c new file mode 100644 index 00000000000..20adfd11690 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3568/syscon_rk3568.c @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2021 Rockchip Electronics Co., Ltd + */ + +#include <common.h> +#include <dm.h> +#include <syscon.h> +#include <asm/arch-rockchip/clock.h> + +static const struct udevice_id rk3568_syscon_ids[] = { + { .compatible = "rockchip,rk3568-grf", .data = ROCKCHIP_SYSCON_GRF }, + { .compatible = "rockchip,rk3568-pmugrf", .data = ROCKCHIP_SYSCON_PMUGRF }, + { } +}; + +U_BOOT_DRIVER(syscon_rk3568) = { + .name = "rk3568_syscon", + .id = UCLASS_SYSCON, + .of_match = rk3568_syscon_ids, +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + .bind = dm_scan_fdt_dev, +#endif +}; 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