diff options
| author | Lokesh Vutla <lokeshvutla@ti.com> | 2017-12-29 11:47:47 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-01-19 15:49:25 -0500 |
| commit | e18cd3d7963dd513b750b35bafe6bfe5b0b038a5 (patch) | |
| tree | f993633a3bd8f334cf2487dfd351a0848413aa6a /arch/arm/mach-omap2/emif-common.c | |
| parent | 72b7af5a04afc22913e943decc1733a25b8eefcf (diff) | |
arm: emif-common: Add ecc specific emif registers
This is a slight difference in emif_ddr_phy_status register offsets for
DRA7xx EMIF and older versions. And ecc registers are available only
in DRA7xx EMIC. Add support for this difference and ecc registers.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/emif-common.c')
| -rw-r--r-- | arch/arm/mach-omap2/emif-common.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mach-omap2/emif-common.c b/arch/arm/mach-omap2/emif-common.c index def7fe0f0a8..2b03dbecf42 100644 --- a/arch/arm/mach-omap2/emif-common.c +++ b/arch/arm/mach-omap2/emif-common.c @@ -255,7 +255,7 @@ static void update_hwleveling_output(u32 base, const struct emif_regs *regs) u32 *emif_ext_phy_ctrl_reg, *emif_phy_status; u32 reg, i, phy; - emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[7]; + emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[6]; phy = readl(&emif->emif_ddr_phy_ctrl_1); /* Update PHY_REG_RDDQS_RATIO */ @@ -269,7 +269,7 @@ static void update_hwleveling_output(u32 base, const struct emif_regs *regs) /* Update PHY_REG_FIFO_WE_SLAVE_RATIO */ emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2; - emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[12]; + emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[11]; if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK)) for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) { reg = readl(emif_phy_status++); @@ -279,7 +279,7 @@ static void update_hwleveling_output(u32 base, const struct emif_regs *regs) /* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */ emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12; - emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[17]; + emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[16]; if (!(phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK)) for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) { reg = readl(emif_phy_status++); |