diff options
| author | Pali Rohár <pali@kernel.org> | 2021-07-31 14:22:52 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2021-08-11 08:42:26 +0200 |
| commit | 29795302b942e6ee41c9d95f7e6e29f57d108d42 (patch) | |
| tree | 7b13994c6545e80bcf5ed4ccba3e34620e49bd68 /arch/arm/mach-mvebu | |
| parent | 293a8de6fa0fdc70f6de6d7fb8d70d46e342e42c (diff) | |
arm: mvebu: a38x: Detect CONFIG_SYS_TCLK from SAR register
Bit 15 in SAR register specifies if TCLK is running at 200 MHz or 250 MHz.
Use this information instead of manual configuration in every board file.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch/arm/mach-mvebu')
| -rw-r--r-- | arch/arm/mach-mvebu/include/mach/soc.h | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 3f3b15aa8a..cb323aa59a 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -33,11 +33,6 @@ #define MV_88F68XX_A0_ID 0x4 #define MV_88F68XX_B0_ID 0xa -/* TCLK Core Clock definition */ -#ifndef CONFIG_SYS_TCLK -#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ -#endif - /* SOC specific definations */ #define INTREG_BASE 0xd0000000 #define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080) @@ -170,6 +165,9 @@ #define BOOT_FROM_SPI 0x32 #define BOOT_FROM_MMC 0x30 #define BOOT_FROM_MMC_ALT 0x31 + +#define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(15)) ? \ + 200000000 : 250000000) #elif defined(CONFIG_ARMADA_MSYS) /* SAR values for MSYS */ #define CONFIG_SAR_REG (MBUS_DFX_BASE + 0xf8200) @@ -207,4 +205,9 @@ #define BOOT_FROM_SPI 0x3 #endif +/* TCLK Core Clock definition */ +#ifndef CONFIG_SYS_TCLK +#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ +#endif + #endif /* _MVEBU_SOC_H */ |