diff options
| author | Chris Packham <judge.packham@gmail.com> | 2019-04-11 22:22:51 +1200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2019-04-12 07:04:18 +0200 |
| commit | 689f9cf6aa9edff89c4d4d3b843f500fc5582300 (patch) | |
| tree | 0141bd7ff9b551fbda4b56a830751ddbe31a78fe /arch/arm/mach-mvebu | |
| parent | 0d0df46ee7323506df2e38738c52d68699c2abca (diff) | |
arm: mvebu: NAND clock support for MSYS devices
One difference with the integrated CPUs is that they use a different
clock control block to the Armada devices. Update mvebu_get_nand_clock()
accordingly.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch/arm/mach-mvebu')
| -rw-r--r-- | arch/arm/mach-mvebu/cpu.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-mvebu/include/mach/soc.h | 11 |
2 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 9868462867..c5b3df46aa 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -499,6 +499,8 @@ u32 mvebu_get_nand_clock(void) if (mvebu_soc_family() == MVEBU_SOC_A38X) reg = MVEBU_DFX_DIV_CLK_CTRL(1); + else if (mvebu_soc_family() == MVEBU_SOC_MSYS) + reg = MVEBU_DFX_DIV_CLK_CTRL(8); else reg = MVEBU_CORE_DIV_CLK_CTRL(1); diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 2d88c410b8..f666ee2424 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -100,9 +100,20 @@ #define SPI_PUP_EN BIT(5) #define MVEBU_CORE_DIV_CLK_CTRL(i) (MVEBU_CLOCK_BASE + ((i) * 0x8)) +#ifdef CONFIG_ARMADA_MSYS +#define MVEBU_DFX_DIV_CLK_CTRL(i) (MVEBU_DFX_BASE + 0xf8000 + 0x250 + ((i) * 0x4)) +#define NAND_ECC_DIVCKL_RATIO_OFFS 6 +#define NAND_ECC_DIVCKL_RATIO_MASK (0xF << NAND_ECC_DIVCKL_RATIO_OFFS) +#else #define MVEBU_DFX_DIV_CLK_CTRL(i) (MVEBU_DFX_BASE + 0x250 + ((i) * 0x4)) +#endif +#ifdef CONFIG_ARMADA_MSYS +#define NAND_ECC_DIVCKL_RATIO_OFFS 6 +#define NAND_ECC_DIVCKL_RATIO_MASK (0xF << NAND_ECC_DIVCKL_RATIO_OFFS) +#else #define NAND_ECC_DIVCKL_RATIO_OFFS 8 #define NAND_ECC_DIVCKL_RATIO_MASK (0x3F << NAND_ECC_DIVCKL_RATIO_OFFS) +#endif #define SDRAM_MAX_CS 4 #define SDRAM_ADDR_MASK 0xFF000000 |