diff options
| author | Nishanth Menon <nm@ti.com> | 2016-03-23 10:14:18 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-04-01 17:17:40 -0400 |
| commit | 1f807a9f32aaa4e4917336912fd867671954d18c (patch) | |
| tree | 6f6b9dc97a360acc5be70a269b5de3380c754be3 /arch/arm/mach-keystone/init.c | |
| parent | e320f0bc9b81076e4c59d281dff1428df5324809 (diff) | |
ARM: keystone2: Refactor MSMC macros to avoid #ifdeffery
MSMC segment Privilege ID is not consistent accross the keystone2 SoCs.
As the first step to ensure complete SoC wide coherency setup, lets
refactor the macros to remove the #if-deffery around the code which
obfuscates which IDs are actually enabled for which SoC.
As a result of this change the PCIe configuration is moved after the
msmc configuration is complete, but that should ideally have no
functional impact.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/mach-keystone/init.c')
| -rw-r--r-- | arch/arm/mach-keystone/init.c | 43 |
1 files changed, 36 insertions, 7 deletions
diff --git a/arch/arm/mach-keystone/init.c b/arch/arm/mach-keystone/init.c index aadd10bff2..2368315ff6 100644 --- a/arch/arm/mach-keystone/init.c +++ b/arch/arm/mach-keystone/init.c @@ -96,22 +96,51 @@ static void config_pcie_mode(int pcie_port, enum pci_mode mode) __raw_writel(val, KS2_DEVCFG); } +static void msmc_k2hkle_common_setup(void) +{ + msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_ARM); + msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_NETCP); +#ifdef KS2_MSMC_SEGMENT_QM_PDSP + msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_QM_PDSP); +#endif + msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_PCIE0); +} + +static inline void msmc_k2l_setup(void) +{ + msmc_share_all_segments(K2L_MSMC_SEGMENT_PCIE1); +} + +static inline void msmc_k2e_setup(void) +{ + msmc_share_all_segments(K2E_MSMC_SEGMENT_PCIE1); +} + +static inline void msmc_k2g_setup(void) +{ + msmc_share_all_segments(K2G_MSMC_SEGMENT_ARM); + msmc_share_all_segments(K2G_MSMC_SEGMENT_NSS); + msmc_share_all_segments(K2G_MSMC_SEGMENT_PCIE); +} + int arch_cpu_init(void) { chip_configuration_unlock(); icache_enable(); - msmc_share_all_segments(KS2_MSMC_SEGMENT_TETRIS); - msmc_share_all_segments(KS2_MSMC_SEGMENT_NETCP); -#ifdef KS2_MSMC_SEGMENT_QM_PDSP - msmc_share_all_segments(KS2_MSMC_SEGMENT_QM_PDSP); -#endif - msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE0); + if (cpu_is_k2g()) { + msmc_k2g_setup(); + } else { + msmc_k2hkle_common_setup(); + if (cpu_is_k2e()) + msmc_k2e_setup(); + else if (cpu_is_k2l()) + msmc_k2l_setup(); + } /* Initialize the PCIe-0 to work as Root Complex */ config_pcie_mode(0, ROOTCOMPLEX); #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L) - msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE1); /* Initialize the PCIe-1 to work as Root Complex */ config_pcie_mode(1, ROOTCOMPLEX); #endif |