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author | Emanuele Ghidoli <emanuele.ghidoli@toradex.com> | 2024-04-10 11:58:31 +0200 |
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committer | Emanuele Ghidoli <emanuele.ghidoli@toradex.com> | 2024-04-25 10:16:25 +0200 |
commit | 3c1274e4347c1326f61191808aa2d3139e6007cd (patch) | |
tree | 7da2e981cb663f966138a736a5f349bba1cdce72 /arch/arm/mach-k3/am62p5_init.c | |
parent | f5306ddb679bfa530f2049059295f3dcf05b4107 (diff) |
arm: k3: j784s4: Fix call to spl_enable_dcache by calling spl_enable_cache
Since commit [1] spl_enable_dcache is no more available and,
at the same time, by enabling instruction cache, boot time is reduced.
[1] 536d0d5eef24 ("arm: k3: Enable instruction cache for main domain SPL")
Upstream-Status: Inappropriate
Commit [1] is already upstreamed. am62p5 and j784s4 were introduced
afterwards and they are using the new function.
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Diffstat (limited to 'arch/arm/mach-k3/am62p5_init.c')
-rw-r--r-- | arch/arm/mach-k3/am62p5_init.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-k3/am62p5_init.c b/arch/arm/mach-k3/am62p5_init.c index 08ad6cfee1..8ce92d506f 100644 --- a/arch/arm/mach-k3/am62p5_init.c +++ b/arch/arm/mach-k3/am62p5_init.c @@ -184,7 +184,7 @@ void board_init_f(ulong dummy) if (ret) panic("DRAM init failed: %d\n", ret); #endif - spl_enable_dcache(); + spl_enable_cache(); debug("am62px_init: %s done\n", __func__); } |