diff options
| author | Ye Li <ye.li@nxp.com> | 2019-01-21 00:33:38 -0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2019-01-21 19:36:21 -0800 |
| commit | 9dada8a697b1c103fdb28f528f168da7ecc20849 (patch) | |
| tree | 3e81f22610b08ba05bc34f866062fa6482f47185 /arch/arm/mach-imx | |
| parent | 1a66350d1baeef355d51da609c505aebb233cefb (diff) | |
MLK-20784-2 imx8mm: Load fuse for TMU TCALIV and TASR
On iMX8MM, the default value of TMU registers TCALIV and TASR need
be loaded from fuse. HW won't do this, it expect SW loads them before
using TMU.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Diffstat (limited to 'arch/arm/mach-imx')
| -rw-r--r-- | arch/arm/mach-imx/imx8m/soc.c | 26 |
1 files changed, 25 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 640f503b9e..ff7b16e086 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -1,5 +1,5 @@ /* - * Copyright 2017-2018 NXP + * Copyright 2017-2019 NXP * * Peng Fan <peng.fan@nxp.com> * @@ -712,3 +712,27 @@ int imx8m_usb_power(int usb_id, bool on) #endif return 0; } + +void nxp_tmu_arch_init(void *reg_base) +{ + if (is_imx8mm()) { + /* Load TCALIV and TASR from fuses */ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[3]; + struct fuse_bank3_regs *fuse = + (struct fuse_bank3_regs *)bank->fuse_regs; + + u32 tca_rt, tca_hr, tca_en; + u32 buf_vref, buf_slope; + + tca_rt = fuse->ana0 & 0xFF; + tca_hr = (fuse->ana0 & 0xFF00) >> 8; + tca_en = (fuse->ana0 & 0x2000000) >> 25; + + buf_vref = (fuse->ana0 & 0x1F00000) >> 20; + buf_slope = (fuse->ana0 & 0xF0000) >> 16; + + writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28); + writel((tca_en << 31) |(tca_hr <<16) | tca_rt, (ulong)reg_base + 0x30); + } +} |