LFU-330-27 arm: imx9: Add SoC support for FEC and EQOS

Add SoC level support for FEC and eQOS controller.

1. Enable the FEC_QUIRK_ENET_MAC
2. Add clock interfaces for eQOS and FEC. eQoS and FEC work with REF CLK
   set to 250M. Because between CCM and ENET, there is a 1/2 divider
3. Set Wakeup AXI clock to 312.5Mhz, because FEC MDIO bus clock has
   a range for its clock divider (64 max), for 333Mhz AXI clock, it will
   overflow.
4. Add eQOS GPR registers, which is need to set RGMII and clock generation

Signed-off-by: Ye Li <ye.li@nxp.com>

2 files changed, 86 insertions, 2 deletions

diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index ce53fbbd9d1..b73135e0290 100644
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -621,8 +621,8 @@ int clock_init(void)
 	ccm_clk_root_cfg(BUS_AON_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
 	/* M33 to 200M */
 	ccm_clk_root_cfg(M33_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2);
-	/* WAKEUP_AXI to 333M */
-	ccm_clk_root_cfg(WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD0, 3);
+	/* WAKEUP_AXI to 312.5M, because of FEC only can support to 320M for generating MII clock at 2.5M  */
+	ccm_clk_root_cfg(WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD2, 2);
 	/* SWO TRACE to 133M */
 	ccm_clk_root_cfg(SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
 	/* M33 systetick to 133M */
@@ -649,6 +649,80 @@ int clock_init(void)
 	return 0;
 }
 
+int set_clk_eqos(enum enet_freq type)
+{
+	u32 eqos_post_div;
+
+	switch (type) {
+	case ENET_125MHZ:
+		eqos_post_div = 2; /* 250M clock */
+		break;
+	case ENET_50MHZ:
+		eqos_post_div = 5; /* 100M clock */
+		break;
+	case ENET_25MHZ:
+		eqos_post_div = 10; /* 50M clock*/
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* disable the clock first */
+	ccm_lpcg_on(CCGR_ENETQOS, false);
+
+	ccm_clk_root_cfg(ENET_CLK_ROOT, SYS_PLL_PFD0_DIV2, eqos_post_div);
+	ccm_clk_root_cfg(ENET_TIMER2_CLK_ROOT, SYS_PLL_PFD0_DIV2, 5);
+
+	/* enable clock */
+	ccm_lpcg_on(CCGR_ENETQOS, true);
+
+	return 0;
+}
+
+u32 imx_get_eqos_csr_clk(void)
+{
+	return ccm_clk_root_get_rate(WAKEUP_AXI_CLK_ROOT);
+}
+
+u32 imx_get_fecclk(void)
+{
+	return ccm_clk_root_get_rate(WAKEUP_AXI_CLK_ROOT);
+}
+
+int set_clk_enet(enum enet_freq type)
+{
+	u32 div;
+
+	/* disable the clock first */
+	ccm_lpcg_on(CCGR_ENET1, false);
+
+	switch (type) {
+	case ENET_125MHZ:
+		div = 2; /* 250Mhz */
+		break;
+	case ENET_50MHZ:
+		div = 5; /* 100Mhz */
+		break;
+	case ENET_25MHZ:
+		div = 10; /* 50Mhz */
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	ccm_clk_root_cfg(ENET_REF_CLK_ROOT, SYS_PLL_PFD0_DIV2, div);
+	ccm_clk_root_cfg(ENET_TIMER1_CLK_ROOT, SYS_PLL_PFD0_DIV2, 5);
+
+#ifdef CONFIG_FEC_MXC_25M_REF_CLK
+	ccm_clk_root_cfg(ENET_REF_PHY_CLK_ROOT, SYS_PLL_PFD0_DIV2, 20);
+#endif
+
+	/* enable clock */
+	ccm_lpcg_on(CCGR_ENET1, true);
+
+	return 0;
+}
+
 /*
  * Dump some clockes.
  */
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index c0f0c5c18d2..1f940d13f3c 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -249,6 +249,16 @@ int dram_init(void)
 	return 0;
 }
 
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+	mac[0] = 0x1;
+	mac[1] = 0x2;
+	mac[2] = 0x3;
+	mac[3] = 0x4;
+	mac[4] = 0x5;
+	mac[5] = 0x6;
+}
+
 int print_cpuinfo(void)
 {
 	u32 cpurev;