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authorPeng Fan <peng.fan@nxp.com>2019-07-22 01:25:05 +0000
committerStefano Babic <sbabic@denx.de>2019-10-08 16:35:16 +0200
commite25dc290aa85ea3b68000295e352681acfa53617 (patch)
treeea2f24b9b352688ea1e521f5b094ae7a7d065504 /arch/arm/mach-imx
parenteae4e0f3c10967386382b848ef80d9f8852d67a1 (diff)
i.MX7ULP: Add CPU revision check for B0
Since there is no register for CPU revision, we use ROM version to check the A0 or B0 chip. Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch/arm/mach-imx')
-rw-r--r--arch/arm/mach-imx/mx7ulp/soc.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c
index 7119ee4a077..6c53aa106e7 100644
--- a/arch/arm/mach-imx/mx7ulp/soc.c
+++ b/arch/arm/mach-imx/mx7ulp/soc.c
@@ -18,10 +18,13 @@ struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
};
#endif
+#define ROM_VERSION_ADDR 0x80
u32 get_cpu_rev(void)
{
- /* Temporally hard code the CPU rev to 0x73, rev 1.0. Fix it later */
- return (MXC_CPU_MX7ULP << 12) | (1 << 4);
+ /* Check the ROM version for cpu revision */
+ u32 rom_version = readl((void __iomem *)ROM_VERSION_ADDR);
+
+ return (MXC_CPU_MX7ULP << 12) | (rom_version & 0xFF);
}
#ifdef CONFIG_REVISION_TAG