Merge tag 'lf-5.15.71-2.2.2' into toradex_imx_lf_v2022.04

This pulls in the following commits:
git log --oneline --no-merges  ^HEAD lf-5.15.71-2.2.2

14b6c8f3e3b MA-20886 imx8ulp: Boot from recovery mode when pressing key
62ad7799b6c LF-7602: Device tree fixup based on compatible string
b35420da607 crypto: fsl_hash: Remove unnecessary alignment check in caam_hash()
918dbf78bbb MA-20872 Revert "MA-18775 system will hang about 3s when boot up kernel"
ed2c3cbd6ac MA-20814 add fastboot command to erase u-boot env
a6762e28bf0 LF-6627: nand drvier fixups in sdboot on ls1043ardb-pd
d23cfa09767 LFU-426: qspihdr: Coverity Issue: unchecked return value
413b08f841f MLK-25850: imx8dxl_ddr3l_evk: change the default fdt file name
e91a047f54f LF-7382: fastboot: improve emmc write speed
205680f9f4b LFU-428 imx8ulp: Add warning for CAAM non-secure state failure
f405551dcc1 LF-7369-2 clk: imx93: update LPCG control API
676831be672 LF-7369-1 clk: imx: implement a clock gate driver for i.MX93
94c5bb2eb83 MA-20507-7 trusty: fix dereference null return value
6933487b4df LFU-427 imx93: Print ELE FW version
15b1ebb00cc LFU-393 imx93: Add reset cause print
f3b75e3317d LF-7332 imx8/ahab: sha256: enable image verification using ARMv8 crypto extention
330e2634143 LFU-423: usb: cdns3: gadget: Avoid using usb_ss after null check
58ba744cbad MLK-26034 imx6: Disable LCDIF clock before jumping to kernel
ae396d343a3 LF-6627: nand drvier fixups in nandboot on ls1043ardb-pd
0a99627b60e LFU-422-2 imx8ulp_evk: Enable the GD25LX256E support
c6c06de038f LFU-422-1 mtd: spi-nor: Add GigaDevice GD25LX256E NOR flash
032fab5e127 LFU-421 imx93_evk: Add imx93 low drive mode support on 11x11 EVK
d9f477625d3 LF-7332 armv8: SHA-256 using ARMv8 Crypto Extensions
53689e4f7db MA-20667 set metadata partition of type f2fs
f824cd01955 LFU-415 net: fec_mxc: Skip recv packet process when fec is halted
4e7c44e1f33 LFU-419 arm: dts: imx8mp: fix flexspi nand reg
957bdd9c925 LFU-418 imx8ulp: upower_hal: make code cleaner
361b23b98ed Revert "MLK-25478-1 efi: add Platform-Reset-Attack variables"
e1ed0611b5e Revert "MLK-25478-2 efi: clean memory and reset MemoryOverwriteRequestControl"
4998fef38a5 Revert "MLK-25478-3 workaround: disable verify time of signer and signee."
320096439b6 MA-20738 imx8ulp: bumps CONFIG_LMB_MAX_REGIONS
c244bdfd76c LFU-417-2 imx93_evk/qsb: Enable DDR inline ECC feature
026521c7d65 LFU-417-1 ddr: imx: imx9: Add DDR inline ECC support
a555a21be69 LFU-413 imx8ulp_evk: Remove CONFIG_BOOTDELAY=0 from ND defconfig
aaead5a2b8d LFU-416 imx: cmd_dek: Fix build warning in blob_encap_dek
933a3b25fe3 LF-7234 enable CONFIG_CMD_CRC32 and CONFIG_CRC32_VERIFY
97fc905e7f7 LFU-409: imx8dxl: fix the i.MX8DXL ddr3l NAND DQS iomux setting
aa4ebb66199 LFU-414 imx8ulp: clock: Update clocks to meet max rate restrictions
63d0579f397 LFU-410 imx: ele_ahab: Add ahab_sec_fuse_prog command
266dddae454 LFU-412 configs: imx93_evk: shrink mem= for jailhouse
5703d3ae37e LFU-411 imx8ulp: Always enable MIPI_DSI power switch
32965eb52f7 LFU-392 imx8ulp: upower: replace magic number with macro
beb5e5e3303 MA-20677 imx8ulp: android: enable CONFIG_AHAB_BOOT by default
bb45dd592db LFU-408 imx93evk: config the pmic standby voltage for buck1
25e38cb4762 LFU-407-02 ddr: imx9: Change the saved ddr data base to 0x2051c000
a8fef10ab92 LFU-407-01 configs: imx93: Update spl stack & bss base address
8731024fe7e LFU-406 mx6ul/mx6ulz: Fix build break caused by RNG patch
a95afe08769 LF-7238 imx9: soc: Remove OPTEE memory from DRAM bank and MMU
19c3fdebf8d LFU-403-4 imx93_evk/qsb: Enable TMU sensor driver
e1703ec06a4 LFU-403-3 iMX93: soc: print current CPU temperature
050a94e6365 LFU-403-2 DTS: imx93: Update TMU node to sync with kernel
91e711a565c LFU-403-1 thermal: imx_tmu: Update TMU driver to support iMX93
78749666dd3 LFU-402-3 imx93_evk/qsb: Use API to set max ARM clock
401b9824f92 LFU-402-2 iMX93: clock: Add API to set max ARM core clock
e4722baa5af LFU-402-1 iMX93: soc: Get market segment and speed grading
432a4af9608 LFU-400 imx8ulp: clock: Clear dividers in PLL3DIV_PFD registers
53f06207782 LFU-399 imx8ulp: Reconfigure MRC3 for SRAM0 access
48a2221acc9 LFU-395 imx93: Add fused parts support
d8760a74793 LFU-398-7 imx93_9x9_qsb: Enable Flexspi NOR support
1f500a59670 LFU-398-6 imx93_qsb: Enable M.2 VPCIe_3V3 and deassert SD3_nRST
ba4f72198f5 LFU-398-5 DTS: imx93-9x9-qsb: Add flexspi NOR nodes and pinctrl
d9f563336f7 LFU-398-4 imx93_11x11_evk: Enable Flexspi NOR support
c56f2132d53 LFU-398-3 imx93_evk: Enable M.2 VPCIe_3V3 and deassert SD3_nRST
b6cbe6b1416 LFU-398-2 DTS: imx93-11x11-evk: Enable and update flexspi NOR
c45c4fb791b LFU-398-1 DTS: imx93: Update flexspi node in DTSi
fab973fe1df LFU-397 imx8m: clock: not configure reserved SRC register
4881ba99fa4 LFU-396-7 imx93_9x9_qsp_defconfig: support splash screen
60e0e629f99 LFU-396-6 arm: dts: add imx93 9x9 ontat panel dts
fffc330cf1a LFU-396-5 imx9: clock: add 300MHz fracn pll table
ef6a3d9cc38 LFU-396-4 video: nxp: imx: add Add i.MX93 parallel display format encoder driver
5f414738a5f LFU-396-3 video: nxp: imx_lcdifv3: support VSYNC/HSYNC active low
21eb66fe1f8 LFU-396-2 video: nxp: imx: dsi: force DISPLAY_FLAGS_HSYNC_HIGH & DISPLAY_FLAGS_VSYNC_HIGH
88132ed0b4e LFU-396-1 video: simple_panel: make backlight optional
65287dc074d LF-7055: video: imx: Add set_parent calls to LVDS initialization
167f65006fb MLK-26021 imx93: add 9x9 qsb lpddr4 board
0a6297a290e MA-20677 imx8ulp: android: enable CONFIG_AHAB_BOOT by default
8789f3ca3e4 PLATSEC-1781-2 MX6: Device tree fix-up
60555c4a445 PLATSEC-1781-1 mx6ull:Add config CONFIG_OF_SYSTEM_SETUP
48b1d6e34fd MA-20149 set fs type of android partitions
9710cc4840e LFOPTEE-177 imx93evk: enable cmd_dek command
f0721d67f03 LFOPTEE-177 imx8ulp: enable cmd_dek command
bf07f5166bf LFOPTEE-177 imx: cmd_dek: add ELE DEK Blob generation support
6de56c3f629 LFOPTEE-177 s400_api: add DEK Blob generation

Conflicts:
	drivers/crypto/fsl/fsl_hash.c
	commit 41b2182af73 ("crypto: fsl_hash: Remove unnecessary
	alignment check in caam_hash()")
	Both NXP and TXD branch did cherry-picking that commit, but NXP
	additionally removed a debug print (not present in master)
	while the TDX branch did not. Resolved by doing it the NXP way.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>

1 files changed, 72 insertions, 7 deletions

diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index 7dc33941a9..909a770e1c 100644
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -26,6 +26,7 @@ static struct anatop_reg *ana_regs = (struct anatop_reg *)ANATOP_BASE_ADDR;
 static struct imx_intpll_rate_table imx9_intpll_tbl[] = {
 	INT_PLL_RATE(1800000000U, 1, 150, 2), /* 1.8Ghz */
 	INT_PLL_RATE(1700000000U, 1, 141, 2), /* 1.7Ghz */
+	INT_PLL_RATE(1500000000U, 1, 125, 2), /* 1.5Ghz */
 	INT_PLL_RATE(1400000000U, 1, 175, 3), /* 1.4Ghz */
 	INT_PLL_RATE(1000000000U, 1, 166, 4), /* 1000Mhz */
 	INT_PLL_RATE(900000000U, 1, 150, 4), /* 900Mhz */
@@ -39,6 +40,7 @@ static struct imx_fracpll_rate_table imx9_fracpll_tbl[] = {
 	FRAC_PLL_RATE(445333333U, 1, 167, 9, 0, 1),
 	FRAC_PLL_RATE(466000000U, 1, 155, 8, 1, 3), /* 466Mhz */
 	FRAC_PLL_RATE(400000000U, 1, 200, 12, 0, 1), /* 400Mhz */
+	FRAC_PLL_RATE(300000000U, 1, 150, 12, 0, 1),
 };
 
 /* return in khz */
@@ -539,6 +541,25 @@ u32 get_arm_core_clk(void)
 	return ccm_clk_root_get_rate(ARM_A55_CLK_ROOT);
 }
 
+void set_arm_core_max_clk(void)
+{
+	u32 speed;
+
+	/* Increase ARM clock to max rate according to speed grade */
+	speed = get_cpu_speed_grade_hz();
+
+	ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_CCM);
+	configure_intpll(ARM_PLL_CLK, speed);
+	ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_PLL);
+}
+
+void set_arm_core_low_drive_clk(void)
+{
+	ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_CCM);
+	configure_intpll(ARM_PLL_CLK, 900000000);
+	ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_PLL);
+}
+
 unsigned int mxc_get_clock(enum mxc_clock clk)
 {
 	switch (clk) {
@@ -611,21 +632,26 @@ void init_uart_clk(u32 index)
 
 void init_clk_usdhc(u32 index)
 {
-	/* 400 Mhz */
+	u32 div;
+	if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE))
+		div = 3; /* 266.67 Mhz */
+	else
+		div = 2; /* 400 Mhz */
+
 	switch (index) {
 	case 0:
 		ccm_lpcg_on(CCGR_USDHC1, 0);
-		ccm_clk_root_cfg(USDHC1_CLK_ROOT, SYS_PLL_PFD1, 2);
+		ccm_clk_root_cfg(USDHC1_CLK_ROOT, SYS_PLL_PFD1, div);
 		ccm_lpcg_on(CCGR_USDHC1, 1);
 		break;
 	case 1:
 		ccm_lpcg_on(CCGR_USDHC2, 0);
-		ccm_clk_root_cfg(USDHC2_CLK_ROOT, SYS_PLL_PFD1, 2);
+		ccm_clk_root_cfg(USDHC2_CLK_ROOT, SYS_PLL_PFD1, div);
 		ccm_lpcg_on(CCGR_USDHC2, 1);
 		break;
 	case 2:
 		ccm_lpcg_on(CCGR_USDHC3, 0);
-		ccm_clk_root_cfg(USDHC3_CLK_ROOT, SYS_PLL_PFD1, 2);
+		ccm_clk_root_cfg(USDHC3_CLK_ROOT, SYS_PLL_PFD1, div);
 		ccm_lpcg_on(CCGR_USDHC3, 1);
 		break;
 	default:
@@ -684,7 +710,36 @@ void dram_disable_bypass(void)
 }
 #endif
 
-int clock_init(void)
+void bus_clock_init_low_drive(void)
+{
+	/* Set A55 clk to 500M */
+	ccm_clk_root_cfg(ARM_A55_CLK_ROOT, SYS_PLL_PFD0, 2);
+	/* Set A55 periphal to 200M */
+	ccm_clk_root_cfg(ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD1, 4);
+	/* Set A55 mtr bus to 133M */
+	ccm_clk_root_cfg(ARM_A55_MTR_BUS_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+
+	/* Sentinel to 133M */
+	ccm_clk_root_cfg(SENTINEL_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+	/* Bus_wakeup to 133M */
+	ccm_clk_root_cfg(BUS_WAKEUP_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+	/* Bus_AON to 133M */
+	ccm_clk_root_cfg(BUS_AON_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+	/* M33 to 133M */
+	ccm_clk_root_cfg(M33_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+	/* WAKEUP_AXI to 200M  */
+	ccm_clk_root_cfg(WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD1, 4);
+	/* SWO TRACE to 133M */
+	ccm_clk_root_cfg(SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+	/* M33 systetick to 24M */
+	ccm_clk_root_cfg(M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1);
+	/* NIC to 250M */
+	ccm_clk_root_cfg(NIC_CLK_ROOT, SYS_PLL_PFD0, 4);
+	/* NIC_APB to 133M */
+	ccm_clk_root_cfg(NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+}
+
+void bus_clock_init(void)
 {
 	/* Set A55 periphal to 333M */
 	ccm_clk_root_cfg(ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD0, 3);
@@ -703,12 +758,22 @@ int clock_init(void)
 	ccm_clk_root_cfg(WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD2, 2);
 	/* SWO TRACE to 133M */
 	ccm_clk_root_cfg(SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
-	/* M33 systetick to 133M */
-	ccm_clk_root_cfg(M33_SYSTICK_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+	/* M33 systetick to 24M */
+	ccm_clk_root_cfg(M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1);
 	/* NIC to 400M */
 	ccm_clk_root_cfg(NIC_CLK_ROOT, SYS_PLL_PFD1, 2);
 	/* NIC_APB to 133M */
 	ccm_clk_root_cfg(NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+}
+
+int clock_init(void)
+{
+	if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)){
+		bus_clock_init_low_drive();
+		set_arm_core_low_drive_clk();
+	} else {
+		bus_clock_init();
+	}
 
 	/* allow for non-secure access */
 	int i;