diff options
| author | Ye Li <ye.li@nxp.com> | 2021-10-25 10:59:20 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2022-07-18 13:55:17 +0800 |
| commit | 49338b3ffd80f9f4f672ee0bfdd445340d0b591b (patch) | |
| tree | a935b16303a59a614cabaed9d8cc34bb7eb93478 /arch/arm/mach-imx/imx8ulp | |
| parent | c1ca49235a0b006d304892d365e414571d7f8a60 (diff) | |
MLK-25979-3 imx8ulp: xrdc: Set MRC4/5 for access DDR from A35 and APD PER
iMX8ULP A1 S400 ROM will remove the setting for MRC4/5. So we have to set
them in SPL to allow access to DDR from A35 and APD PER masters
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch/arm/mach-imx/imx8ulp')
| -rw-r--r-- | arch/arm/mach-imx/imx8ulp/rdc.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c index 6d2adcfca6..caf19357d8 100644 --- a/arch/arm/mach-imx/imx8ulp/rdc.c +++ b/arch/arm/mach-imx/imx8ulp/rdc.c @@ -276,6 +276,15 @@ void xrdc_init_mda(void) void xrdc_init_mrc(void) { + /* Set MRC4 and MRC5 for DDR access from A35 and AP NIC PER masters */ + xrdc_config_mrc_w0_w1(4, 0, CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE); + xrdc_config_mrc_dx_perm(4, 0, 7, 1); + xrdc_config_mrc_w3_w4(4, 0, 0x0, 0x80000FFF); + + xrdc_config_mrc_w0_w1(5, 0, CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE); + xrdc_config_mrc_dx_perm(5, 0, 1, 1); + xrdc_config_mrc_w3_w4(5, 0, 0x0, 0x80000FFF); + /* The MRC8 is for SRAM1 */ xrdc_config_mrc_w0_w1(8, 0, 0x21000000, 0x10000); /* Allow for all domains: So domain 2/3 (HIFI DSP/LPAV) is ok to access */ |