diff options
| author | Teo Hall <teo.hall@nxp.com> | 2020-02-06 08:57:33 -0600 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2022-04-06 18:03:30 +0800 |
| commit | b0e655444d97a303e3eb555a9a1fde9723506f7f (patch) | |
| tree | b2563e4e731b45dae70b95fd317257bc1ebbd916 /arch/arm/mach-imx/imx8 | |
| parent | b809a962a85b3f1824306a2c2abedde323219e30 (diff) | |
MLK-23279-2 imx: Add support for i.MX8DXL SoC
Add clocks required for new i.MX8DXL SoC. Since most of clocks are
same as iMX8QXP, share the same driver but with iMX8DXL new clocks added.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Teo Hall <teo.hall@nxp.com>
(cherry picked from commit f9c23b2df504c5db5f8f4567ee4c92f2439308fc)
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit dc7b8a6b97258e7a46a014e5b866cac55ad617f7)
(cherry picked from commit f4ce88dfe557dc87f3a107b32b9b6126f58160f7)
(cherry picked from commit eddd8eb01a307fa840a5a7a22bf6bd4e52330450)
Diffstat (limited to 'arch/arm/mach-imx/imx8')
| -rw-r--r-- | arch/arm/mach-imx/imx8/clock.c | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/arch/arm/mach-imx/imx8/clock.c b/arch/arm/mach-imx/imx8/clock.c index cb9ec2090f..645225e4c2 100644 --- a/arch/arm/mach-imx/imx8/clock.c +++ b/arch/arm/mach-imx/imx8/clock.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2018-2019 NXP + * Copyright 2018-2020 NXP */ #include <common.h> @@ -354,6 +354,8 @@ void init_clk_fec(int index) * so finally RGMII TX clk is 125Mhz */ rate = 250000000; + if (is_imx8dxl() && index == 1) /* eQos */ + rate = 125000000; /* div = 8 clk_source = PLL_1 ss_slice #7 in verfication codes */ err = sc_pm_set_clock_rate(-1, enet[index], 2, &rate); @@ -372,11 +374,13 @@ void init_clk_fec(int index) } /* Configure GPR regisers */ - if (sc_misc_set_control(-1, enet[index], SC_C_TXCLK, 0) != SC_ERR_NONE) - printf("\nConfigure GPR registers operation(%d) failed!\n", SC_C_TXCLK); - /* Enable divclk */ - if (sc_misc_set_control(-1, enet[index], SC_C_CLKDIV, 1) != SC_ERR_NONE) - printf("\nConfigure GPR registers operation(%d) failed!\n", SC_C_CLKDIV); + if (!(is_imx8dxl() && index == 1)) { + if (sc_misc_set_control(-1, enet[index], SC_C_TXCLK, 0) != SC_ERR_NONE) + printf("\nConfigure GPR registers operation(%d) failed!\n", SC_C_TXCLK); + /* Enable divclk */ + if (sc_misc_set_control(-1, enet[index], SC_C_CLKDIV, 1) != SC_ERR_NONE) + printf("\nConfigure GPR registers operation(%d) failed!\n", SC_C_CLKDIV); + } if (sc_misc_set_control(-1, enet[index], SC_C_DISABLE_50, 1) != SC_ERR_NONE) printf("\nConfigure GPR registers operation(%d) failed!\n", SC_C_DISABLE_50); if (sc_misc_set_control(-1, enet[index], SC_C_DISABLE_125, 1) != SC_ERR_NONE) |