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authorWenyou Yang <wenyou.yang@atmel.com>2016-02-01 18:18:21 +0800
committerAndreas Bießmann <andreas.devel@googlemail.com>2016-02-02 11:49:13 +0100
commit37dadbca0c8b9bff00f892fd87a978cbe0a98b3a (patch)
tree5d1ef0331ab89ab5934c7f8b06d812ef09d29627 /arch/arm/mach-at91
parent4245701ef58c9c7c1dbccc8fa2f1bdd248b97b8b (diff)
board: atmel: sama5d2_xplained: add SPL support
The sama5d2 Xplained SPL supports the boot medias: spi flash and SD Card. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Diffstat (limited to 'arch/arm/mach-at91')
-rw-r--r--arch/arm/mach-at91/Kconfig1
-rw-r--r--arch/arm/mach-at91/Makefile1
-rw-r--r--arch/arm/mach-at91/include/mach/sama5d2.h32
3 files changed, 34 insertions, 0 deletions
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index c33364758bd..9426302b38c 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -74,6 +74,7 @@ config TARGET_AT91SAM9X5EK
config TARGET_SAMA5D2_XPLAINED
bool "SAMA5D2 Xplained board"
select CPU_V7
+ select SUPPORT_SPL
config TARGET_SAMA5D3_XPLAINED
bool "SAMA5D3 Xplained board"
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 5b89617623e..abd1d13da7e 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o
obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o
obj-$(CONFIG_AT91SAM9N12) += mpddrc.o spl_at91.o
obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o
+obj-$(CONFIG_SAMA5D2) += mpddrc.o spl_atmel.o matrix.o atmel_sfr.o
obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o
obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o matrix.o atmel_sfr.o
obj-y += spl.o
diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h
index c85571c999e..dd5a2a7523d 100644
--- a/arch/arm/mach-at91/include/mach/sama5d2.h
+++ b/arch/arm/mach-at91/include/mach/sama5d2.h
@@ -106,6 +106,7 @@
#define ATMEL_BASE_MPDDRC 0xf000c000
#define ATMEL_BASE_XDMAC0 0xf0010000
#define ATMEL_BASE_PMC 0xf0014000
+#define ATMEL_BASE_MATRIX0 0xf0018000
#define ATMEL_BASE_QSPI0 0xf0020000
#define ATMEL_BASE_QSPI1 0xf0024000
#define ATMEL_BASE_SPI0 0xf8000000
@@ -117,6 +118,7 @@
#define ATMEL_BASE_UART1 0xf8020000
#define ATMEL_BASE_UART2 0xf8024000
#define ATMEL_BASE_TWI0 0xf8028000
+#define ATMEL_BASE_SFR 0xf8030000
#define ATMEL_BASE_SYSC 0xf8048000
#define ATMEL_BASE_SPI1 0xfc000000
#define ATMEL_BASE_UART3 0xfc008000
@@ -125,6 +127,7 @@
#define ATMEL_BASE_UDPHS 0xfc02c000
#define ATMEL_BASE_PIOA 0xfc038000
+#define ATMEL_BASE_MATRIX1 0xfc03c000
#define ATMEL_CHIPID_CIDR 0xfc069000
#define ATMEL_CHIPID_EXID 0xfc069004
@@ -171,6 +174,35 @@
#define CPU_HAS_PCR
#define CPU_HAS_H32MXDIV
+/* AICREDIR Unlock Key */
+#define ATMEL_SFR_AICREDIR_KEY 0xB6D81C4D
+
+/* MATRIX0(H64MX) slave id definitions */
+#define H64MX_SLAVE_AXIMX_BRIDGE 0 /* Bridge from H64MX to AXIMX */
+#define H64MX_SLAVE_PERIPH_BRIDGE 1 /* H64MX Peripheral Bridge */
+#define H64MX_SLAVE_DDRC_PORT0 2 /* DDR2 Port0-AESOTF */
+#define H64MX_SLAVE_DDRC_PORT1 3 /* DDR2 Port1 */
+#define H64MX_SLAVE_DDRC_PORT2 4 /* DDR2 Port2 */
+#define H64MX_SLAVE_DDRC_PORT3 5 /* DDR2 Port3 */
+#define H64MX_SLAVE_DDRC_PORT4 6 /* DDR2 Port4 */
+#define H64MX_SLAVE_DDRC_PORT5 7 /* DDR2 Port5 */
+#define H64MX_SLAVE_DDRC_PORT6 8 /* DDR2 Port6 */
+#define H64MX_SLAVE_DDRC_PORT7 9 /* DDR2 Port7 */
+#define H64MX_SLAVE_SRAM 10 /* Internal SRAM 128K */
+#define H64MX_SLAVE_CACHE_L2 11 /* Internal SRAM 128K(L2) */
+#define H64MX_SLAVE_QSPI0 12 /* QSPI0 */
+#define H64MX_SLAVE_QSPI1 13 /* QSPI1 */
+#define H64MX_SLAVE_AESB 14 /* AESB */
+
+/* MATRIX1(H32MX) slave id definitions */
+#define H32MX_SLAVE_H64MX_BRIDGE 0 /* Bridge from H32MX to H64MX */
+#define H32MX_SLAVE_PERIPH_BRIDGE0 1 /* H32MX Peripheral Bridge 0 */
+#define H32MX_SLAVE_PERIPH_BRIDGE1 2 /* H32MX Peripheral Bridge 1 */
+#define H32MX_SLAVE_EBI 3 /* External Bus Interface */
+#define H32MX_SLAVE_NFC_CMD 3 /* NFC command Register */
+#define H32MX_SLAVE_NFC_SRAM 4 /* NFC SRAM */
+#define H32MX_SLAVE_USB 5 /* USB Device & Host */
+
/* SAMA5D2 series chip id definitions */
#define ARCH_ID_SAMA5D2 0x8a5c08c0
#define ARCH_EXID_SAMA5D21CU 0x0000005a