diff options
author | Simon Glass <sjg@chromium.org> | 2011-04-26 10:52:37 -0700 |
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committer | Simon Glass <sjg@chromium.org> | 2011-08-24 09:54:53 -0700 |
commit | 84d99e6f30b19c4b9006bb199bad2fab078ce222 (patch) | |
tree | 38c887237632190cf3d2902e303efc680ecda316 /arch/arm/lib | |
parent | 2b3e03dde5601c3826b79e173b2d6bfdc3792237 (diff) |
Tegra2: Enable data cache
This plumbs in support for the Cortex A9's data cache. Since armv7
instructions are used we need to ensure that none of these appear in the
instruction stream executed by the ARM7TDMI.
BUG=chromium-os:12253
TEST=build and boot U-Boot on Seaboard, check that it makes it to Linux
Tegra2 (SeaBoard) # dcache
Data (writethrough) Cache is ON
Tegra2 (SeaBoard) #
Change-Id: I91e6ef847abcb821dcaf482faa31d82b98ba93b8
Reviewed-on: http://gerrit.chromium.org/gerrit/198
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm/lib')
-rw-r--r-- | arch/arm/lib/board.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 6347d71112..b7a6a4ee6a 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -277,6 +277,15 @@ void board_init_f (ulong bootflag) /* compiler optimization barrier needed for GCC >= 3.4 */ __asm__ __volatile__("": : :"memory"); +#ifdef CONFIG_TEGRA2 + /* + * Call this now in case we are running on the AVP, since it doesn't + * support the BLX instruction generated by the init sequence. It + * won't return on AVP, since the AVP halts and the A9 CPU wakes up + * and starts at its reset vector, etc. + */ + board_early_init_f(); +#endif memset ((void*)gd, 0, sizeof (gd_t)); gd->mon_len = _bss_end_ofs; |