diff options
author | Simon Glass <sjg@chromium.org> | 2011-06-07 11:12:37 -0700 |
---|---|---|
committer | Simon Glass <sjg@chromium.org> | 2011-08-29 10:39:16 -0700 |
commit | 09aaff19dc440ce967e125392cb7014279db830b (patch) | |
tree | 1f837497969820492f47b64abf8dc15db5080d0b /arch/arm/lib/cache-cp15.c | |
parent | ad828a69c4ea6d882fd1a822e4a6c25e2d3f075d (diff) |
Add control over cachability of memory regions
This is needed for LCD support, where we want to make the LCD frame buffer
write-through (or off) rather than write-back.
BUG=chromium-os:14082
TEST=build U-Boot
Change-Id: I7e1bf9358b8c2fb7ae524cc74cdcfa5b0fb60fbe
Reviewed-on: http://gerrit.chromium.org/gerrit/2239
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm/lib/cache-cp15.c')
-rw-r--r-- | arch/arm/lib/cache-cp15.c | 54 |
1 files changed, 43 insertions, 11 deletions
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index b1ccc3ce0a6..cc40124d8ce 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -26,12 +26,6 @@ #if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE)) -#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) -#define CACHE_SETUP 0x1a -#else -#define CACHE_SETUP 0x1e -#endif - DECLARE_GLOBAL_DATA_PTR; void __arm_init_before_mmu(void) @@ -50,9 +44,44 @@ static void cp_delay (void) asm volatile("" : : : "memory"); } -static inline void dram_bank_mmu_setup(int bank) +void set_section_dcache(int section, enum dcache_option option) { + u32 value = section << MMU_SECTION_SHIFT | (3 << 10); u32 *page_table = (u32 *)gd->tlb_addr; + + switch (option) { + case DCACHE_WRITETHROUGH: + value |= 0x1a; + break; + + case DCACHE_WRITEBACK: + value |= 0x1e; + break; + + case DCACHE_OFF: + value |= 0x12; + break; + } + + page_table[section] = value; +} + +void mmu_set_region_dcache(u32 start, int size, enum dcache_option option) +{ + u32 *page_table = (u32 *)gd->tlb_addr; + u32 upto, end; + + end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT; + start = start >> MMU_SECTION_SHIFT; + debug("mmu_set_region_dcache start=%x, size=%x, option=%d\n", + start, size, option); + for (upto = start; upto < end; upto++) + set_section_dcache(upto, option); + mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]); +} + +static inline void dram_bank_mmu_setup(int bank) +{ bd_t *bd = gd->bd; int i; @@ -60,21 +89,24 @@ static inline void dram_bank_mmu_setup(int bank) for (i = bd->bi_dram[bank].start >> 20; i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20; i++) { - page_table[i] = i << 20 | (3 << 10) | CACHE_SETUP; +#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) + set_section_dcache(i, DCACHE_WRITETHROUGH); +#else + set_section_dcache(i, DCACHE_WRITEBACK); +#endif } } /* to activate the MMU we need to set up virtual memory: use 1M areas */ static inline void mmu_setup(void) { - u32 *page_table = (u32 *)gd->tlb_addr; int i; u32 reg; arm_init_before_mmu(); /* Set up an identity-mapping for all 4GB, rw for everyone */ for (i = 0; i < 4096; i++) - page_table[i] = i << 20 | (3 << 10) | 0x12; + set_section_dcache(i, DCACHE_OFF); for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { dram_bank_mmu_setup(i); @@ -82,7 +114,7 @@ static inline void mmu_setup(void) /* Copy the page table address to cp15 */ asm volatile("mcr p15, 0, %0, c2, c0, 0" - : : "r" (page_table) : "memory"); + : : "r" (gd->tlb_addr) : "memory"); /* Set the access control to all-supervisor */ asm volatile("mcr p15, 0, %0, c3, c0, 0" : : "r" (~0)); |