diff options
| author | Ye Li <ye.li@nxp.com> | 2018-12-05 20:00:25 -0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2018-12-11 21:49:23 -0800 |
| commit | 484104758d3c2f98d3c9ae493f778b1427e2630c (patch) | |
| tree | 83b3f0243c282acca11a75234a5e00a6a010ac80 /arch/arm/include | |
| parent | 19f234266e07c18ab8364336779bf2d3d1f51c81 (diff) | |
MLK-20528-2 imx8: Enable clocks LPCG
To support partition reboot, the u-boot has to enable clocks by LPCG.
The LPCG will reset to default value only when the subsystem is totally
power off and reset. However, the resources in one subsystem may belong
to different partitions, so the partition reboot may not reboot the entire
subsystem.
Powers, clocks/lpcg, GPR, IP may not reset depends on various cases and
HW design. Thus, AP software has to ensure everything is reset by SW
itself to support such above cases.
Signed-off-by: Ye Li <ye.li@nxp.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-imx8/i2c.h | 47 |
1 files changed, 29 insertions, 18 deletions
diff --git a/arch/arm/include/asm/arch-imx8/i2c.h b/arch/arm/include/asm/arch-imx8/i2c.h index 4c88b9f5d7..6506efffda 100644 --- a/arch/arm/include/asm/arch-imx8/i2c.h +++ b/arch/arm/include/asm/arch-imx8/i2c.h @@ -8,29 +8,40 @@ #define __ASM_ARCH_IMX8_I2C_H__ #include <asm/mach-imx/sci/sci.h> +#include <asm/arch/lpcg.h> struct imx_i2c_map { - int index; + unsigned index; sc_rsrc_t rsrc; + u32 lpcg[4]; }; static struct imx_i2c_map imx_i2c_desc[] = { - {0, SC_R_I2C_0}, - {1, SC_R_I2C_1}, - {2, SC_R_I2C_2}, - {3, SC_R_I2C_3}, - {4, SC_R_I2C_4}, - {5, SC_R_LVDS_0_I2C_0}, /* lvds0 i2c0 */ - {6, SC_R_LVDS_0_I2C_0}, /* lvds0 i2c1 */ - {7, SC_R_LVDS_1_I2C_0}, /* lvds1 i2c0 */ - {8, SC_R_LVDS_1_I2C_0}, /* lvds1 i2c1 */ - {9, SC_R_CSI_0_I2C_0}, - {10, SC_R_CSI_1_I2C_0}, - {11, SC_R_HDMI_I2C_0}, - {12, SC_R_HDMI_RX_I2C_0}, - {13, SC_R_MIPI_0_I2C_0}, - {14, SC_R_MIPI_0_I2C_1}, - {15, SC_R_MIPI_1_I2C_0}, - {16, SC_R_MIPI_1_I2C_1}, + {0, SC_R_I2C_0, {LPI2C_0_LPCG}}, + {1, SC_R_I2C_1, {LPI2C_1_LPCG}}, + {2, SC_R_I2C_2, {LPI2C_2_LPCG}}, + {3, SC_R_I2C_3, {LPI2C_3_LPCG}}, +#ifdef CONFIG_IMX8QM + {4, SC_R_I2C_4, {LPI2C_4_LPCG}}, +#endif + {5, SC_R_LVDS_0_I2C_0, {DI_LVDS_0_LPCG + 0x10}}, /* lvds0 i2c0 */ + {6, SC_R_LVDS_0_I2C_0, {DI_LVDS_0_LPCG + 0x10}}, /* lvds0 i2c1 */ + {7, SC_R_LVDS_1_I2C_0, {DI_LVDS_1_LPCG + 0x10}}, /* lvds1 i2c0 */ + {8, SC_R_LVDS_1_I2C_0, {DI_LVDS_1_LPCG + 0x10}}, /* lvds1 i2c1 */ + {9, SC_R_CSI_0_I2C_0, {MIPI_CSI_0_LPCG + 0x14}}, + {10, SC_R_CSI_1_I2C_0, {MIPI_CSI_1_LPCG + 0x14}}, + {11, SC_R_HDMI_I2C_0, {DI_HDMI_LPCG}}, + {12, SC_R_HDMI_RX_I2C_0, {RX_HDMI_LPCG + 0x10, RX_HDMI_LPCG + 0x14, RX_HDMI_LPCG + 0x18, RX_HDMI_LPCG + 0x1C}}, +#ifdef CONFIG_IMX8QM + {13, SC_R_MIPI_0_I2C_0, {MIPI_DSI_0_LPCG + 0x14, MIPI_DSI_0_LPCG + 0x18, MIPI_DSI_0_LPCG + 0x1c}}, + {14, SC_R_MIPI_0_I2C_1, {MIPI_DSI_0_LPCG + 0x24, MIPI_DSI_0_LPCG + 0x28, MIPI_DSI_0_LPCG + 0x2c}}, + {15, SC_R_MIPI_1_I2C_0, {MIPI_DSI_1_LPCG + 0x14, MIPI_DSI_1_LPCG + 0x18, MIPI_DSI_1_LPCG + 0x1c}}, + {16, SC_R_MIPI_1_I2C_1, {MIPI_DSI_1_LPCG + 0x24, MIPI_DSI_1_LPCG + 0x28, MIPI_DSI_1_LPCG + 0x2c}}, +#else + {13, SC_R_MIPI_0_I2C_0, {DI_MIPI0_LPCG, DI_MIPI0_LPCG + 0x10, DI_MIPI0_LPCG + 0x14}}, + {14, SC_R_MIPI_0_I2C_1, {DI_MIPI0_LPCG, DI_MIPI0_LPCG + 0x10, DI_MIPI0_LPCG + 0x14}}, + {15, SC_R_MIPI_1_I2C_0, {DI_MIPI1_LPCG, DI_MIPI1_LPCG + 0x10, DI_MIPI1_LPCG + 0x14}}, + {16, SC_R_MIPI_1_I2C_1, {DI_MIPI1_LPCG, DI_MIPI1_LPCG + 0x10, DI_MIPI1_LPCG + 0x14}}, +#endif }; #endif /* __ASM_ARCH_IMX8_I2C_H__ */ |