diff options
| author | Lukasz Majewski <lukma@denx.de> | 2018-12-05 17:04:01 +0100 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2019-02-15 12:16:50 +0100 |
| commit | c5b22a5360662597511bebf95058c9dc777ee788 (patch) | |
| tree | 393e736ed8af37f466434b7a22c10dd8a198449b /arch/arm/include | |
| parent | 63f7e3fca391a50a499fed828fe16325fdee45f3 (diff) | |
ddr: vybrid: Add DDRMC calibration related registers (DQS to DQ)
This commit provides extra defines needed for DDR memory controller
calibration (read leveling performing).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Agner <stefan.agner@toradex.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-vf610/imx-regs.h | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index f71fbf4e73..5d1f63c98b 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -207,15 +207,27 @@ #define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16) #define DDRMC_CR89_AODT_RWSMCS(v) ((v) & 0xf) #define DDRMC_CR91_R2W_SMCSDL(v) (((v) & 0x7) << 16) +#define DDRMC_CR93_SW_LVL_MODE_OFF (8) +#define DDRMC_CR93_SW_LVL_MODE(v) (((v) & 0x3) << DDRMC_CR93_SW_LVL_MODE_OFF) +#define DDRMC_CR93_SWLVL_LOAD BIT(16) +#define DDRMC_CR93_SWLVL_START BIT(24) +#define DDRMC_CR94_SWLVL_EXIT BIT(0) +#define DDRMC_CR94_SWLVL_OP_DONE BIT(8) +#define DDRMC_CR94_SWLVL_RESP_0_OFF (24) +#define DDRMC_CR95_SWLVL_RESP_1_OFF (0) #define DDRMC_CR96_WLMRD(v) (((v) & 0x3f) << 8) #define DDRMC_CR96_WLDQSEN(v) ((v) & 0x3f) #define DDRMC_CR97_WRLVL_EN (1 << 24) #define DDRMC_CR98_WRLVL_DL_0(v) ((v) & 0xffff) #define DDRMC_CR99_WRLVL_DL_1(v) ((v) & 0xffff) +#define DDRMC_CR101_PHY_RDLVL_EDGE_OFF (24) +#define DDRMC_CR101_PHY_RDLVL_EDGE BIT(DDRMC_CR101_PHY_RDLVL_EDGE_OFF) #define DDRMC_CR102_RDLVL_GT_REGEN (1 << 16) #define DDRMC_CR102_RDLVL_REG_EN (1 << 8) -#define DDRMC_CR105_RDLVL_DL_0(v) (((v) & 0xff) << 8) +#define DDRMC_CR105_RDLVL_DL_0_OFF (8) +#define DDRMC_CR105_RDLVL_DL_0(v) (((v) & 0xff) << DDRMC_CR105_RDLVL_DL_0_OFF) #define DDRMC_CR106_RDLVL_GTDL_0(v) ((v) & 0xff) +#define DDRMC_CR110_RDLVL_DL_1_OFF (0) #define DDRMC_CR110_RDLVL_DL_1(v) ((v) & 0xff) #define DDRMC_CR110_RDLVL_GTDL_1(v) (((v) & 0xff) << 16) #define DDRMC_CR114_RDLVL_GTDL_2(v) (((v) & 0xffff) << 8) |