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authorNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>2014-01-08 10:14:26 +0900
committerNobuhiro Iwamatsu <iwamatsu@nigauri.org>2014-01-16 08:07:20 +0900
commit82852762ced9e08db3062394020f87bf0b1812b8 (patch)
treec522ffe7c504be1f344cf2d0d62d7ef46a1a6830 /arch/arm/include
parent16bf36f77931393965c8a2fdd62f441f93de0b67 (diff)
arm: rmobile: Add SH QSPI base register address
This adds base register address of SH QSPI. Currently, SH QSPI is used only from R8A7790 and R8A7791. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/arch-rmobile/r8a7790.h1
-rw-r--r--arch/arm/include/asm/arch-rmobile/r8a7791.h1
2 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7790.h b/arch/arm/include/asm/arch-rmobile/r8a7790.h
index 42d65d356da..d9ea71fa14f 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7790.h
+++ b/arch/arm/include/asm/arch-rmobile/r8a7790.h
@@ -19,6 +19,7 @@
#define DBSC3_1_BASE 0xE67A0000
#define TMU_BASE 0xE61E0000
#define GPIO5_BASE 0xE6055000
+#define SH_QSPI_BASE 0xE6B10000
#define S3C_BASE 0xE6784000
#define S3C_INT_BASE 0xE6784A00
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7791.h b/arch/arm/include/asm/arch-rmobile/r8a7791.h
index 2afda0a62f7..ff301805914 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7791.h
+++ b/arch/arm/include/asm/arch-rmobile/r8a7791.h
@@ -19,6 +19,7 @@
#define DBSC3_1_BASE 0xE67A0000
#define TMU_BASE 0xE61E0000
#define GPIO5_BASE 0xE6055000
+#define SH_QSPI_BASE 0xE6B10000
#define S3C_BASE 0xE6784000
#define S3C_INT_BASE 0xE6784A00