diff options
| author | Haibo Chen <haibo.chen@nxp.com> | 2018-03-14 17:15:23 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2020-04-26 23:24:29 -0700 |
| commit | 70aae62ef4e42b08aa4b5b31d4e467af3eb47dc4 (patch) | |
| tree | 1302ab6aa06781285b24f92c620e7b0dbea2ad88 /arch/arm/include | |
| parent | 19b6ca6c6cb2afe154001804fedc830ff4f9d505 (diff) | |
MLK-17586-3 i.MX7ULP: change USDHC clock rate
Change USDHC0 and USDHC1 per clock source from APLL_PFD1,
and set the APll_PFD1 clock rate to 352.8MHz.
Also gate off APll_PFD1/2/3 before boot OS, otherwise set
the clock rate of APll_PFD1/2/3 during OS boot up will triger
some warning message.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
(cherry picked from commit 07ef0fab23204684d82f27baf721a72b247f30c5)
(cherry picked from commit 1c30a73542990afbe48bf7a398baba9c5efaf4fe)
(cherry picked from commit 0e4ce4b6b3f8d06f5b63850e04a1e4deb9b07624)
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-mx7ulp/scg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-mx7ulp/scg.h b/arch/arm/include/asm/arch-mx7ulp/scg.h index b79bde338f4..72b4dc7d8ec 100644 --- a/arch/arm/include/asm/arch-mx7ulp/scg.h +++ b/arch/arm/include/asm/arch-mx7ulp/scg.h @@ -325,6 +325,7 @@ typedef struct scg_regs { u32 scg_clk_get_rate(enum scg_clk clk); int scg_enable_pll_pfd(enum scg_clk clk, u32 frac); +int scg_disable_pll_pfd(enum scg_clk clk); int scg_enable_usb_pll(bool usb_control); u32 decode_pll(enum pll_clocks pll); |