diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2014-10-24 17:06:07 +0200 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2014-10-28 09:41:23 +0100 |
| commit | c7497b0fff4f086bccd13b8d408800d2f27419ee (patch) | |
| tree | dc56e079efc1bb32eb93f3bc6e363563449faa9a /arch/arm/include/asm | |
| parent | 7d71154703be65ebb48676427780f69b72160acb (diff) | |
arm: vf610: extract leveling parameter in a struct
DDR leveling parameters are board specific, hence we should be able
to set them differently per board. Extract the leveling parameters
in a seperate struct to be able to set them per board.
Diffstat (limited to 'arch/arm/include/asm')
| -rw-r--r-- | arch/arm/include/asm/arch-vf610/ddr-vf610.h | 15 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-vf610/imx-regs.h | 6 |
2 files changed, 16 insertions, 5 deletions
diff --git a/arch/arm/include/asm/arch-vf610/ddr-vf610.h b/arch/arm/include/asm/arch-vf610/ddr-vf610.h index 6c1cf6adce..e56d94dc75 100644 --- a/arch/arm/include/asm/arch-vf610/ddr-vf610.h +++ b/arch/arm/include/asm/arch-vf610/ddr-vf610.h @@ -8,8 +8,21 @@ #ifndef __ASM_ARCH_VF610_DDR_H #define __ASM_ARCH_VF610_DDR_H +struct ddr_lvl_info { + u16 wrlvl_reg_en; + u16 wrlvl_dl_0; + u16 wrlvl_dl_1; + u16 rdlvl_gt_reg_en; + u16 rdlvl_gt_dl_0; + u16 rdlvl_gt_dl_1; + u16 rdlvl_reg_en; + u16 rdlvl_dl_0; + u16 rdlvl_dl_1; +}; + void setup_iomux_ddr(void); void ddr_phy_init(void); -void ddr_ctrl_init(int tref, int trfc, int col_diff, int row_diff); +void ddr_ctrl_init(int tref, int trfc, int col_diff, int row_diff, + struct ddr_lvl_info *lvl); #endif diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index 2341e9d342..c510842b9c 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -198,16 +198,14 @@ #define DDRMC_CR96_WLMRD(v) (((v) & 0x3f) << 8) #define DDRMC_CR96_WLDQSEN(v) ((v) & 0x3f) #define DDRMC_CR97_WRLVL_EN (1 << 24) -#define DDRMC_CR98_WRLVL_DL_0 (0) -#define DDRMC_CR99_WRLVL_DL_1 (0) +#define DDRMC_CR98_WRLVL_DL_0(v) ((v) & 0xffff) +#define DDRMC_CR99_WRLVL_DL_1(v) ((v) & 0xffff) #define DDRMC_CR102_RDLVL_GT_REGEN (1 << 16) #define DDRMC_CR102_RDLVL_REG_EN (1 << 8) #define DDRMC_CR105_RDLVL_DL_0(v) (((v) & 0xff) << 8) #define DDRMC_CR106_RDLVL_GTDL_0(v) ((v) & 0xff) #define DDRMC_CR110_RDLVL_DL_1(v) ((v) & 0xff) #define DDRMC_CR110_RDLVL_GTDL_1(v) (((v) & 0xff) << 16) -#define DDRMC_CR114_RDLVL_GTDL_2(v) (((v) & 0xffff) << 8) -#define DDRMC_CR115_RDLVL_GTDL_2(v) ((v) & 0xff) #define DDRMC_CR117_AXI0_W_PRI(v) (((v) & 0x3) << 8) #define DDRMC_CR117_AXI0_R_PRI(v) ((v) & 0x3) #define DDRMC_CR118_AXI1_W_PRI(v) (((v) & 0x3) << 24) |