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authorAnthony Felice <tony.felice@timesys.com>2014-09-06 19:47:06 +0200
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2014-10-07 13:08:31 +0200
commitc19a8bc5711ec63e905ef91f045a1489f0aa3cb0 (patch)
treea29aaf854053be0d81157e8ee1dc106cc9956b8d /arch/arm/include/asm/imx-common
parent1454ba8e56d88a8b95ac8050cde2c07c651cd0ae (diff)
vf610twr: Tune DDR initialization settings
Removed settings in unsupported register fields. They didn’t do anything, and in most cases, were not documented in the reference manual. Changed register settings to comply with JEDEC required values. Changed timing parameters because they included full clock periods that were doing nothing. Signed-off-by: Anthony Felice <tony.felice@timesys.com> [rebased on v2014.10-rc2] Signed-off-by: Stefan Agner <stefan@agner.ch>
Diffstat (limited to 'arch/arm/include/asm/imx-common')
-rw-r--r--arch/arm/include/asm/imx-common/iomux-v3.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h
index 70ee86c4321..a8ca49c343f 100644
--- a/arch/arm/include/asm/imx-common/iomux-v3.h
+++ b/arch/arm/include/asm/imx-common/iomux-v3.h
@@ -120,6 +120,8 @@ typedef u64 iomux_v3_cfg_t;
#define PAD_MUX_MODE_SHIFT 20
+#define PAD_CTL_INPUT_DIFFERENTIAL (1 << 16)
+
#define PAD_CTL_SPEED_MED (1 << 12)
#define PAD_CTL_SPEED_HIGH (3 << 12)