diff options
author | David Feng <fenghua@phytium.com.cn> | 2013-12-14 11:47:35 +0800 |
---|---|---|
committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-01-09 16:08:44 +0100 |
commit | 0ae7653128c80a4f2920cbe9b124792c2fd9d9e0 (patch) | |
tree | 14fea7a80e4ea84c7b6a3bc32298daeec55054c7 /arch/arm/include/asm/cache.h | |
parent | 54799e4596bf8af33fd4a8dee153be7011c06d8d (diff) |
arm64: core support
Relocation code based on a patch by Scott Wood, which is:
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: David Feng <fenghua@phytium.com.cn>
Diffstat (limited to 'arch/arm/include/asm/cache.h')
-rw-r--r-- | arch/arm/include/asm/cache.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index 6d60a4a6d95..ddebbc8fcdc 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -11,6 +11,8 @@ #include <asm/system.h> +#ifndef CONFIG_ARM64 + /* * Invalidate L2 Cache using co-proc instruction */ @@ -28,6 +30,9 @@ void l2_cache_disable(void); void set_section_dcache(int section, enum dcache_option option); void dram_bank_mmu_setup(int bank); + +#endif + /* * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We * use that value for aligning DMA buffers unless the board config has specified |