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authorChao Fu <B44548@freescale.com>2014-05-06 09:13:03 +0800
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2014-06-09 09:18:15 +0200
commitcb6d04d60664210d2e198192e164b6cfc8bade83 (patch)
treee8b099002c921a2304bcf31d12210e2f90217c9a /arch/arm/include/asm/arch-vf610/imx-regs.h
parent9d2ca0984bda37bb58bf7f58f1626450e28a6595 (diff)
arm: vf610: Add QSPI support for VF610TWR
Add QSPI support for VF610TWR, such as clock and iomux. Signed-off-by: Alison Wang <Huan.Wang@freescale.com> Signed-off-by: Chao Fu <b44548@freescale.com>
Diffstat (limited to 'arch/arm/include/asm/arch-vf610/imx-regs.h')
-rw-r--r--arch/arm/include/asm/arch-vf610/imx-regs.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
index 0c28e1b840..bd6f680b63 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -87,6 +87,8 @@
#define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000)
#define ENET1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00051000)
+#define QSPI0_AMBA_BASE 0x20000000
+
/* MUX mode and PAD ctrl are in one register */
#define CONFIG_IOMUX_SHARE_CONF_REG