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authorWolfgang Denk <wd@denx.de>2011-06-01 22:04:12 +0200
committerWolfgang Denk <wd@denx.de>2011-06-01 22:04:12 +0200
commit033cd2c42bf335d3b96e9612695f6c30b83dce2b (patch)
tree1bc9e1d9163cd3114bfeb016d4f4311fbbbec491 /arch/arm/include/asm/arch-u8500/u8500.h
parent2130b03309dcf56dab11b6fd0be3b4bedc7f628c (diff)
parentcd3af8b56749b3200cd858b5a9424c6661958e5f (diff)
Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm: SMDKV310: Fix incorrect conditional compilation for MIU linear mapping SMDKV310: CPU fequency and mmc_pre_ratio modified armv7: Add support for ST-Ericsson U8500 href platform I2C: Add driver for ST-Ericsson U8500 i2c armv7: Add ST-Ericsson u8500 arch Kirkwood: boards cleanup for deprecated CONFIG_CMD_AUTOSCRIPT ARMV7: Vexpress: Add missing MMC header arm/km: update mgcoge3un board support mvgbe: enable configurability of PORT_SERIAL_CONTROL_VALUE arm/km: rename mgcoge2un to mgcoge3un arm/km: add second serial interface for kirkwood arm/km: disable ls (through jffs2 support) arm/km: introduce bootcount env variable and clean km_arm arm/km: move CONFIG_EXTRA_ENV_SETTINGS from board to km_arm file arm/km: remove CONFIG_SYS_KWD_CONFIG from keymile-common.h ARMV7: MMC SPL Boot support for SMDKV310 board ARMV7: Add support for Samsung SMDKV310 Board S5PC2XX: clock: support pwm clock for evt1 (cpu revision 1) S5P: add set_mmc_clk for external clock control S5PC2XX: Support the cpu revision S5P:SROM config code moved to s5p-common directory Add _end for the end of u-boot image for SMDK6400 MMC S5P: Fix typo S5P: GPIO Macro Values Corrected. SMDK2410: various cleanup/code style fixes SMDK2410: use the CFI driver (and remove the old one) SMDK2410: remove unneeded config.mk SMDK2410: activate ARM relocation feature BeagleBoard: fixed typo in typecast mvsata: issue hard reset on initialization VCMA9: use ARM relocation feature to fix build error MX31: drop warnings due to missing prototype for mxc_watchdog_reset() MX5: drop config.mk from efikamx board MX31: Make get_reset_cause() static and drop unreachable code MX53: Remove CONFIG_SYS_BOOTMAPSZ from mx53 config files. MX53: Handle silicon revision 2.1 case mx5: board: code clean up for checkboard code MX51: vision2: Fix build for vision2 board. MX51: vision: Let video mode struct be independant of watchdog. MX53: Add initial support for MX53SMD board. MX53: support for freescale MX53LOCO board mx5: Fix CONFIG_OF_LIBFDT redefined warning mx5: Remove unnecessary CONFIG_SYS_BOOTMAPSZ definition mx31pdk: Clean up mx31pdk.h file
Diffstat (limited to 'arch/arm/include/asm/arch-u8500/u8500.h')
-rw-r--r--arch/arm/include/asm/arch-u8500/u8500.h47
1 files changed, 47 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-u8500/u8500.h b/arch/arm/include/asm/arch-u8500/u8500.h
new file mode 100644
index 0000000000..0d6dbb7dbb
--- /dev/null
+++ b/arch/arm/include/asm/arch-u8500/u8500.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2009
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __U8500_H
+#define __U8500_H
+
+/*
+ * base register values for U8500
+ */
+#define CFG_PRCMU_BASE 0x80157000 /* Power, reset and clock
+ Management Unit */
+#define CFG_SDRAMC_BASE 0x903CF000 /* SDRAMC cnf registers */
+#define CFG_FSMC_BASE 0x80000000 /* FSMC Controller */
+
+/*
+ * U8500 GPIO register base for 9 banks
+ */
+#define U8500_GPIO_0_BASE 0x8012E000
+#define U8500_GPIO_1_BASE 0x8012E080
+#define U8500_GPIO_2_BASE 0x8000E000
+#define U8500_GPIO_3_BASE 0x8000E080
+#define U8500_GPIO_4_BASE 0x8000E100
+#define U8500_GPIO_5_BASE 0x8000E180
+#define U8500_GPIO_6_BASE 0x8011E000
+#define U8500_GPIO_7_BASE 0x8011E080
+#define U8500_GPIO_8_BASE 0xA03FE000
+
+#endif /* __U8500_H */