diff options
| author | Varun Wadekar <vwadekar@nvidia.com> | 2012-01-03 15:04:40 +0530 |
|---|---|---|
| committer | Gerrit <chrome-bot@google.com> | 2012-02-08 22:08:36 -0800 |
| commit | 929e867d143b66d96e6c4a8e1f69d3e8c6ca14fd (patch) | |
| tree | 0c28785a6fbed4277223d5882d92c7e8ffc5db8d /arch/arm/include/asm/arch-tegra | |
| parent | f116864a29c5b29ed5b63c6aafc93442ba35f483 (diff) | |
arm: tegra2: split LP0 code to help future chips
split the LP0 code for tegra2 into common
LP0 code and chip specific warm boot code
BUG=chromium-os:23496
TEST=build for Seaboard
Change-Id: Id9756c08f61502affa8beee636d883d01468e6ec
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/13799
Diffstat (limited to 'arch/arm/include/asm/arch-tegra')
| -rw-r--r-- | arch/arm/include/asm/arch-tegra/warmboot.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-tegra/warmboot.h b/arch/arm/include/asm/arch-tegra/warmboot.h index a47b21ef1a..c1a9a15929 100644 --- a/arch/arm/include/asm/arch-tegra/warmboot.h +++ b/arch/arm/include/asm/arch-tegra/warmboot.h @@ -24,6 +24,10 @@ #ifndef _WARM_BOOT_H_ #define _WARM_BOOT_H_ +#define BCT_OFFSET 0x100 /* BCT starts at 0x100 */ +#define BCT_SDRAM_PARAMS_OFFSET (BCT_OFFSET + 0x88) +#define SDRAM_PARAMS_BASE (AP20_BASE_PA_SRAM + BCT_SDRAM_PARAMS_OFFSET) + /* bit fields definitions for APB_MISC_GP_HIDREV register */ #define HIDREV_MINOPREV_RANGE 19 : 16 #define HIDREV_CHIPID_RANGE 15 : 8 |