ICH SPI: Use an atomic preop for Write Enable

The U-boot spi interface uses Software Sequencing and handles
write transactions in three distinct steps:
1) issue Write Enable op
2) issue Page Program op
3) poll Read Status Reg for completion

However in an Intel 6-series chipset the Management Engine is
also issuing a lot of transactions through the same controller
to the same chip.  It is possible for an ME transaction to
occur between the U-boot issuing WREN and sending the actual
data, resulting in the host WREN being lost and the data not
actually being written to the chip.

This change intercepts WREN opcode and instead applies it as
a prefix operator for the next issued transaction, ensuring
that the two are issued back-to-back to the SPI chip.

Unfortunately this register is not writable when the SPI
contoller is locked down, so it is not always applicable.

BUG=chrome-os-partner:6690
TEST=repeated manual testing on lumpy with boot/suspend/resume

Change-Id: I75e353942fd6148a93be561ff422e37dfc6dc8c4
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/11625
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>

0 files changed, 0 insertions, 0 deletions