diff options
| author | Tom Warren <twarren@nvidia.com> | 2011-11-16 16:38:34 -0700 |
|---|---|---|
| committer | Gerrit <chrome-bot@google.com> | 2011-11-18 00:00:45 -0800 |
| commit | 318c9b21768d937e4a8984af86fec6fcd02242f2 (patch) | |
| tree | 7f76b9915570a9e1d1c8d3cf16d318676ba2764b /arch/arm/include/asm/arch-tegra | |
| parent | e0a72afdcd769abd7ac3465d86e45bc0ccd95833 (diff) | |
arm: Tegra3: complete 408MHz PLLP init
Signed-off-by: Tom Warren <twarren@nvidia.com>
BUG=chromium-os:21033
TEST=Built and booted OK on my Waluigi. UART is OK, mmc, spi, i2c OK.
Note that this is only valid with CONFIG_SYS_PLLP_BASE_IS_408MHZ.
No affect on Tegra2. Seaboard builds fine, BTW.
Change-Id: I05a367afd1e78a2170d7308a658ce64017850ca0
Reviewed-on: https://gerrit.chromium.org/gerrit/11811
Tested-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit-Ready: Che-Liang Chiou <clchiou@chromium.org>
Diffstat (limited to 'arch/arm/include/asm/arch-tegra')
| -rw-r--r-- | arch/arm/include/asm/arch-tegra/clk_rst.h | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h index 94811679c8..74af2ea8ca 100644 --- a/arch/arm/include/asm/arch-tegra/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra/clk_rst.h @@ -29,7 +29,7 @@ struct clk_pll { uint pll_base; /* the control register */ uint pll_out; /* output control */ - uint reserved; + uint pll_out_b; /* some have output B control */ uint pll_misc; /* other misc things */ }; @@ -128,6 +128,21 @@ struct clk_rst_ctlr { #define PLLU_VCO_FREQ_RANGE 20:20 #define PLL_VCO_FREQ_RANGE 3:0 +#define PLLP_OUT1_OVR (1 << 2) +#define PLLP_OUT2_OVR (1 << 18) +#define PLLP_OUT3_OVR (1 << 2) +#define PLLP_OUT4_OVR (1 << 18) +#define PLLP_OUT1_RATIO 8 +#define PLLP_OUT2_RATIO 24 +#define PLLP_OUT3_RATIO 8 +#define PLLP_OUT4_RATIO 24 +enum { + IN_408_OUT_204_DIVISOR = 2, + IN_408_OUT_102_DIVISOR = 6, + IN_408_OUT_48_DIVISOR = 15, + IN_408_OUT_9_6_DIVISOR = 83, +}; + /* CLK_RST_CONTROLLER_OSC_CTRL_0 */ #define OSC_FREQ_RANGE 31:30 |