diff options
| author | Tom Warren <twarren@nvidia.com> | 2011-12-02 16:42:52 -0700 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2011-12-13 13:23:32 -0800 |
| commit | 3c48935acca9c4dc554de6119f1b21171275789f (patch) | |
| tree | 69a17e7018685464317251724b12ffc1d2943413 /arch/arm/include/asm/arch-tegra | |
| parent | c509c038d5a8005dc725fbd15a7a631fd997ab48 (diff) | |
tegra: USB: Add T30 USB header files
BUG=chromium-os:23496
TEST=built Seaboard and Waluigi OK
Signed-off-by: Tom Warren <twarren@nvidia.com>
Change-Id: I954cdb71eb80a3cf48f44b9a7183a2cafcb7755b
Reviewed-on: https://gerrit.chromium.org/gerrit/12442
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Commit-Ready: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm/include/asm/arch-tegra')
| -rw-r--r-- | arch/arm/include/asm/arch-tegra/clk_rst.h | 31 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-tegra/tegra.h | 3 |
2 files changed, 29 insertions, 5 deletions
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h index f820581ec7..0c36fbb638 100644 --- a/arch/arm/include/asm/arch-tegra/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra/clk_rst.h @@ -124,13 +124,11 @@ struct clk_rst_ctlr { uint crc_clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX_0, 0x37C */ uint crc_cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL_0, 0x380 */ uint crc_reserved33[11]; /* _reserved_33, 0x384-3ac */ - uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW]; /* _G3D2_0..., 0x3b0-0x42c */ /* _RST_DEV_V/W_SET_0 0x430 ~ 0x43c */ struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW]; /* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */ struct clk_set_clr crc_clk_enb_ex_vw[TEGRA_CLK_REGS_VW]; - uint crc_reserved40[12]; /* _reserved_40, 0x450-47C */ uint crc_pll_cfg0; /* _PLL_CFG0_0, 0x480 */ uint crc_pll_cfg1; /* _PLL_CFG1_0, 0x484 */ @@ -242,4 +240,33 @@ enum { #define CLK_SYS_RATE_APB_RATE_SHIFT 0 #define CLK_SYS_RATE_APB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT) +#if defined(CONFIG_TEGRA3) +/* UTMIP PLL config regs moved from USB to CLK/RST domain on T30 */ +/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 */ +#define UTMIP_PLLU_ENABLE_DLY_COUNT_RANGE 31:27 +#define UTMIP_PLL_SETUP_RANGE 26:18 +#define UTMIP_FORCE_PLLU_POWERUP_RANGE 17:17 +#define UTMIP_FORCE_PLLU_POWERDOWN_RANGE 16:16 +#define UTMIP_FORCE_PLL_ENABLE_POWERUP_RANGE 15:15 +#define UTMIP_FORCE_PLL_ENABLE_POWERDOWN_RANGE 14:14 +#define UTMIP_FORCE_PLL_ACTIVE_POWERUP_RANGE 13:13 +#define UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_RANGE 12:12 +#define UTMIP_XTAL_FREQ_COUNT_RANGE 11:0 + +/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 */ +#define UTMIP_PHY_XTAL_CLOCKEN_RANGE 30:30 +#define UTMIP_FORCE_PD_CLK60_POWERUP_RANGE 29:29 +#define UTMIP_FORCE_PD_CLK60_POWERDOWN_RANGE 28:28 +#define UTMIP_FORCE_PD_CLK48_POWERUP_RANGE 27:27 +#define UTMIP_FORCE_PD_CLK48_POWERDOWN_RANGE 26:26 +#define UTMIP_PLL_ACTIVE_DLY_COUNT_RANGE 23:18 +#define UTMIP_PLLU_STABLE_COUNT_RANGE 17:6 +#define UTMIP_FORCE_PD_SAMP_C_POWERUP_RANGE 5:5 +#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN_RANGE 4:4 +#define UTMIP_FORCE_PD_SAMP_B_POWERUP_RANGE 3:3 +#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN_RANGE 2:2 +#define UTMIP_FORCE_PD_SAMP_A_POWERUP_RANGE 1:1 +#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN_RANGE 0:0 +#endif /* Tegra3 */ + #endif /* CLK_RST_H */ diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h index b7119c00b0..471420136f 100644 --- a/arch/arm/include/asm/arch-tegra/tegra.h +++ b/arch/arm/include/asm/arch-tegra/tegra.h @@ -59,9 +59,6 @@ #define NV_PA_FUSE_BASE 0x7000F800 #define NV_PA_CSITE_BASE 0x70040000 -#define NV_PA_USB1_BASE 0xC5000000 -#define NV_PA_USB3_BASE 0xC5008000 - #define TEGRA_SDRC_CS0 NV_PA_SDRAM_BASE #define LOW_LEVEL_SRAM_STACK 0x4000FFFC #define EARLY_AVP_STACK (NV_PA_SDRAM_BASE + 0x20000) |