diff options
| author | Allen Martin <amartin@nvidia.com> | 2012-08-31 08:30:00 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-09-01 14:58:21 +0200 |
| commit | 00a2749d7be5b0e6cb6435187ec8fea600b44627 (patch) | |
| tree | 3d3107a9b369a09ba5c40abff80d23788939b48d /arch/arm/include/asm/arch-tegra2 | |
| parent | 0d04f34a357d004364b58159b64aad354e65137e (diff) | |
tegra20: rename tegra2 -> tegra20
This is make naming consistent with the kernel and devicetree and in
preparation of pulling out the common tegra20 code.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/include/asm/arch-tegra2')
26 files changed, 0 insertions, 2983 deletions
diff --git a/arch/arm/include/asm/arch-tegra2/ap20.h b/arch/arm/include/asm/arch-tegra2/ap20.h deleted file mode 100644 index d222c44233..0000000000 --- a/arch/arm/include/asm/arch-tegra2/ap20.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * (C) Copyright 2010-2011 - * NVIDIA Corporation <www.nvidia.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include <asm/types.h> - -/* Stabilization delays, in usec */ -#define PLL_STABILIZATION_DELAY (300) -#define IO_STABILIZATION_DELAY (1000) - -#define NVBL_PLLP_KHZ (216000) - -#define PLLX_ENABLED (1 << 30) -#define CCLK_BURST_POLICY 0x20008888 -#define SUPER_CCLK_DIVIDER 0x80000000 - -/* Calculate clock fractional divider value from ref and target frequencies */ -#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2) - -/* Calculate clock frequency value from reference and clock divider value */ -#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2)) - -/* AVP/CPU ID */ -#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */ -#define PG_UP_TAG_0 0x0 - -#define CORESIGHT_UNLOCK 0xC5ACCE55; - -/* AP20-Specific Base Addresses */ - -/* AP20 Base physical address of SDRAM. */ -#define AP20_BASE_PA_SDRAM 0x00000000 -/* AP20 Base physical address of internal SRAM. */ -#define AP20_BASE_PA_SRAM 0x40000000 -/* AP20 Size of internal SRAM (256KB). */ -#define AP20_BASE_PA_SRAM_SIZE 0x00040000 -/* AP20 Base physical address of flash. */ -#define AP20_BASE_PA_NOR_FLASH 0xD0000000 -/* AP20 Base physical address of boot information table. */ -#define AP20_BASE_PA_BOOT_INFO AP20_BASE_PA_SRAM - -/* - * Super-temporary stacks for EXTREMELY early startup. The values chosen for - * these addresses must be valid on ALL SOCs because this value is used before - * we are able to differentiate between the SOC types. - * - * NOTE: The since CPU's stack will eventually be moved from IRAM to SDRAM, its - * stack is placed below the AVP stack. Once the CPU stack has been moved, - * the AVP is free to use the IRAM the CPU stack previously occupied if - * it should need to do so. - * - * NOTE: In multi-processor CPU complex configurations, each processor will have - * its own stack of size CPU_EARLY_BOOT_STACK_SIZE. CPU 0 will have a - * limit of CPU_EARLY_BOOT_STACK_LIMIT. Each successive CPU will have a - * stack limit that is CPU_EARLY_BOOT_STACK_SIZE less then the previous - * CPU. - */ - -/* Common AVP early boot stack limit */ -#define AVP_EARLY_BOOT_STACK_LIMIT \ - (AP20_BASE_PA_SRAM + (AP20_BASE_PA_SRAM_SIZE/2)) -/* Common AVP early boot stack size */ -#define AVP_EARLY_BOOT_STACK_SIZE 0x1000 -/* Common CPU early boot stack limit */ -#define CPU_EARLY_BOOT_STACK_LIMIT \ - (AVP_EARLY_BOOT_STACK_LIMIT - AVP_EARLY_BOOT_STACK_SIZE) -/* Common CPU early boot stack size */ -#define CPU_EARLY_BOOT_STACK_SIZE 0x1000 - -#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100) -#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0) -#define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0) - -#define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4) -#define FLOW_MODE_STOP 2 -#define HALT_COP_EVENT_JTAG (1 << 28) -#define HALT_COP_EVENT_IRQ_1 (1 << 11) -#define HALT_COP_EVENT_FIQ_1 (1 << 9) - -/* Start up the tegra2 SOC */ -void tegra2_start(void); - -/* This is the main entry into U-Boot, used by the Cortex-A9 */ -extern void _start(void); - -/** - * Works out the SOC type used for clocks settings - * - * @return SOC type - see TEGRA_SOC... - */ -int tegra_get_chip_type(void); diff --git a/arch/arm/include/asm/arch-tegra2/apb_misc.h b/arch/arm/include/asm/arch-tegra2/apb_misc.h deleted file mode 100644 index eb69d18d01..0000000000 --- a/arch/arm/include/asm/arch-tegra2/apb_misc.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2012 The Chromium OS Authors. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _GP_PADCTRL_H_ -#define _GP_PADCTRL_H_ - -/* APB_MISC_PP registers */ -struct apb_misc_pp_ctlr { - u32 reserved0[2]; - u32 strapping_opt_a;/* 0x08: APB_MISC_PP_STRAPPING_OPT_A */ -}; - -/* bit fields definitions for APB_MISC_PP_STRAPPING_OPT_A register */ -#define RAM_CODE_SHIFT 4 -#define RAM_CODE_MASK (0xf << RAM_CODE_SHIFT) - -#endif diff --git a/arch/arm/include/asm/arch-tegra2/board.h b/arch/arm/include/asm/arch-tegra2/board.h deleted file mode 100644 index a90d36c708..0000000000 --- a/arch/arm/include/asm/arch-tegra2/board.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _TEGRA_BOARD_H_ -#define _TEGRA_BOARD_H_ - -/* Setup UARTs for the board according to the selected config */ -void board_init_uart_f(void); - -#endif diff --git a/arch/arm/include/asm/arch-tegra2/clk_rst.h b/arch/arm/include/asm/arch-tegra2/clk_rst.h deleted file mode 100644 index 8c3be91514..0000000000 --- a/arch/arm/include/asm/arch-tegra2/clk_rst.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _CLK_RST_H_ -#define _CLK_RST_H_ - -/* PLL registers - there are several PLLs in the clock controller */ -struct clk_pll { - uint pll_base; /* the control register */ - uint pll_out; /* output control */ - uint reserved; - uint pll_misc; /* other misc things */ -}; - -/* PLL registers - there are several PLLs in the clock controller */ -struct clk_pll_simple { - uint pll_base; /* the control register */ - uint pll_misc; /* other misc things */ -}; - -/* - * Most PLLs use the clk_pll structure, but some have a simpler two-member - * structure for which we use clk_pll_simple. The reason for this non- - * othogonal setup is not stated. - */ -enum { - TEGRA_CLK_PLLS = 6, /* Number of normal PLLs */ - TEGRA_CLK_SIMPLE_PLLS = 3, /* Number of simple PLLs */ - TEGRA_CLK_REGS = 3, /* Number of clock enable registers */ - TEGRA_CLK_SOURCES = 64, /* Number of peripheral clock sources */ -}; - -/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */ -struct clk_rst_ctlr { - uint crc_rst_src; /* _RST_SOURCE_0,0x00 */ - uint crc_rst_dev[TEGRA_CLK_REGS]; /* _RST_DEVICES_L/H/U_0 */ - uint crc_clk_out_enb[TEGRA_CLK_REGS]; /* _CLK_OUT_ENB_L/H/U_0 */ - uint crc_reserved0; /* reserved_0, 0x1C */ - uint crc_cclk_brst_pol; /* _CCLK_BURST_POLICY_0,0x20 */ - uint crc_super_cclk_div; /* _SUPER_CCLK_DIVIDER_0,0x24 */ - uint crc_sclk_brst_pol; /* _SCLK_BURST_POLICY_0, 0x28 */ - uint crc_super_sclk_div; /* _SUPER_SCLK_DIVIDER_0,0x2C */ - uint crc_clk_sys_rate; /* _CLK_SYSTEM_RATE_0, 0x30 */ - uint crc_prog_dly_clk; /* _PROG_DLY_CLK_0, 0x34 */ - uint crc_aud_sync_clk_rate; /* _AUDIO_SYNC_CLK_RATE_0,0x38 */ - uint crc_reserved1; /* reserved_1, 0x3C */ - uint crc_cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY_0,0x40 */ - uint crc_clk_mask_arm; /* _CLK_MASK_ARM_0, 0x44 */ - uint crc_misc_clk_enb; /* _MISC_CLK_ENB_0, 0x48 */ - uint crc_clk_cpu_cmplx; /* _CLK_CPU_CMPLX_0, 0x4C */ - uint crc_osc_ctrl; /* _OSC_CTRL_0, 0x50 */ - uint crc_pll_lfsr; /* _PLL_LFSR_0, 0x54 */ - uint crc_osc_freq_det; /* _OSC_FREQ_DET_0, 0x58 */ - uint crc_osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS_0,0x5C */ - uint crc_reserved2[8]; /* reserved_2[8], 0x60-7C */ - - struct clk_pll crc_pll[TEGRA_CLK_PLLS]; /* PLLs from 0x80 to 0xdc */ - - /* PLLs from 0xe0 to 0xf4 */ - struct clk_pll_simple crc_pll_simple[TEGRA_CLK_SIMPLE_PLLS]; - - uint crc_reserved10; /* _reserved_10, 0xF8 */ - uint crc_reserved11; /* _reserved_11, 0xFC */ - - uint crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0... 0x100-1fc */ - uint crc_reserved20[80]; /* 0x200-33C */ - uint crc_cpu_cmplx_set; /* _CPU_CMPLX_SET_0, 0x340 */ - uint crc_cpu_cmplx_clr; /* _CPU_CMPLX_CLR_0, 0x344 */ -}; - -/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */ -#define CPU1_CLK_STP_SHIFT 9 - -#define CPU0_CLK_STP_SHIFT 8 -#define CPU0_CLK_STP_MASK (1U << CPU0_CLK_STP_SHIFT) - -/* CLK_RST_CONTROLLER_PLLx_BASE_0 */ -#define PLL_BYPASS_SHIFT 31 -#define PLL_BYPASS_MASK (1U << PLL_BYPASS_SHIFT) - -#define PLL_ENABLE_SHIFT 30 -#define PLL_ENABLE_MASK (1U << PLL_ENABLE_SHIFT) - -#define PLL_BASE_OVRRIDE_MASK (1U << 28) - -#define PLL_DIVP_SHIFT 20 -#define PLL_DIVP_MASK (7U << PLL_DIVP_SHIFT) - -#define PLL_DIVN_SHIFT 8 -#define PLL_DIVN_MASK (0x3ffU << PLL_DIVN_SHIFT) - -#define PLL_DIVM_SHIFT 0 -#define PLL_DIVM_MASK (0x1f << PLL_DIVM_SHIFT) - -/* CLK_RST_CONTROLLER_PLLx_MISC_0 */ -#define PLL_CPCON_SHIFT 8 -#define PLL_CPCON_MASK (15U << PLL_CPCON_SHIFT) - -#define PLL_LFCON_SHIFT 4 -#define PLL_LFCON_MASK (15U << PLL_LFCON_SHIFT) - -#define PLLU_VCO_FREQ_SHIFT 20 -#define PLLU_VCO_FREQ_MASK (1U << PLLU_VCO_FREQ_SHIFT) - -/* CLK_RST_CONTROLLER_OSC_CTRL_0 */ -#define OSC_FREQ_SHIFT 30 -#define OSC_FREQ_MASK (3U << OSC_FREQ_SHIFT) -#define OSC_XOBP_SHIFT 1 -#define OSC_XOBP_MASK (1U << OSC_XOBP_SHIFT) - -/* - * CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 - the mask here is normally 8 bits - * but can be 16. We could use knowledge we have to restrict the mask in - * the 8-bit cases (the divider_bits value returned by - * get_periph_clock_source()) but it does not seem worth it since the code - * already checks the ranges of values it is writing, in clk_get_divider(). - */ -#define OUT_CLK_DIVISOR_SHIFT 0 -#define OUT_CLK_DIVISOR_MASK (0xffff << OUT_CLK_DIVISOR_SHIFT) - -#define OUT_CLK_SOURCE_SHIFT 30 -#define OUT_CLK_SOURCE_MASK (3U << OUT_CLK_SOURCE_SHIFT) - -#define OUT_CLK_SOURCE4_SHIFT 28 -#define OUT_CLK_SOURCE4_MASK (15U << OUT_CLK_SOURCE4_SHIFT) - -#endif /* CLK_RST_H */ diff --git a/arch/arm/include/asm/arch-tegra2/clock.h b/arch/arm/include/asm/arch-tegra2/clock.h deleted file mode 100644 index ff83bbf293..0000000000 --- a/arch/arm/include/asm/arch-tegra2/clock.h +++ /dev/null @@ -1,407 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* Tegra2 clock control functions */ - -#ifndef _CLOCK_H -#define _CLOCK_H - -/* Set of oscillator frequencies supported in the internal API. */ -enum clock_osc_freq { - /* All in MHz, so 13_0 is 13.0MHz */ - CLOCK_OSC_FREQ_13_0, - CLOCK_OSC_FREQ_19_2, - CLOCK_OSC_FREQ_12_0, - CLOCK_OSC_FREQ_26_0, - - CLOCK_OSC_FREQ_COUNT, -}; - -/* The PLLs supported by the hardware */ -enum clock_id { - CLOCK_ID_FIRST, - CLOCK_ID_CGENERAL = CLOCK_ID_FIRST, - CLOCK_ID_MEMORY, - CLOCK_ID_PERIPH, - CLOCK_ID_AUDIO, - CLOCK_ID_USB, - CLOCK_ID_DISPLAY, - - /* now the simple ones */ - CLOCK_ID_FIRST_SIMPLE, - CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, - CLOCK_ID_EPCI, - CLOCK_ID_SFROM32KHZ, - - /* These are the base clocks (inputs to the Tegra SOC) */ - CLOCK_ID_32KHZ, - CLOCK_ID_OSC, - - CLOCK_ID_COUNT, /* number of clocks */ - CLOCK_ID_NONE = -1, -}; - -/* The clocks supported by the hardware */ -enum periph_id { - PERIPH_ID_FIRST, - - /* Low word: 31:0 */ - PERIPH_ID_CPU = PERIPH_ID_FIRST, - PERIPH_ID_RESERVED1, - PERIPH_ID_RESERVED2, - PERIPH_ID_AC97, - PERIPH_ID_RTC, - PERIPH_ID_TMR, - PERIPH_ID_UART1, - PERIPH_ID_UART2, - - /* 8 */ - PERIPH_ID_GPIO, - PERIPH_ID_SDMMC2, - PERIPH_ID_SPDIF, - PERIPH_ID_I2S1, - PERIPH_ID_I2C1, - PERIPH_ID_NDFLASH, - PERIPH_ID_SDMMC1, - PERIPH_ID_SDMMC4, - - /* 16 */ - PERIPH_ID_TWC, - PERIPH_ID_PWM, - PERIPH_ID_I2S2, - PERIPH_ID_EPP, - PERIPH_ID_VI, - PERIPH_ID_2D, - PERIPH_ID_USBD, - PERIPH_ID_ISP, - - /* 24 */ - PERIPH_ID_3D, - PERIPH_ID_IDE, - PERIPH_ID_DISP2, - PERIPH_ID_DISP1, - PERIPH_ID_HOST1X, - PERIPH_ID_VCP, - PERIPH_ID_RESERVED30, - PERIPH_ID_CACHE2, - - /* Middle word: 63:32 */ - PERIPH_ID_MEM, - PERIPH_ID_AHBDMA, - PERIPH_ID_APBDMA, - PERIPH_ID_RESERVED35, - PERIPH_ID_KBC, - PERIPH_ID_STAT_MON, - PERIPH_ID_PMC, - PERIPH_ID_FUSE, - - /* 40 */ - PERIPH_ID_KFUSE, - PERIPH_ID_SBC1, - PERIPH_ID_SNOR, - PERIPH_ID_SPI1, - PERIPH_ID_SBC2, - PERIPH_ID_XIO, - PERIPH_ID_SBC3, - PERIPH_ID_DVC_I2C, - - /* 48 */ - PERIPH_ID_DSI, - PERIPH_ID_TVO, - PERIPH_ID_MIPI, - PERIPH_ID_HDMI, - PERIPH_ID_CSI, - PERIPH_ID_TVDAC, - PERIPH_ID_I2C2, - PERIPH_ID_UART3, - - /* 56 */ - PERIPH_ID_RESERVED56, - PERIPH_ID_EMC, - PERIPH_ID_USB2, - PERIPH_ID_USB3, - PERIPH_ID_MPE, - PERIPH_ID_VDE, - PERIPH_ID_BSEA, - PERIPH_ID_BSEV, - - /* Upper word 95:64 */ - PERIPH_ID_SPEEDO, - PERIPH_ID_UART4, - PERIPH_ID_UART5, - PERIPH_ID_I2C3, - PERIPH_ID_SBC4, - PERIPH_ID_SDMMC3, - PERIPH_ID_PCIE, - PERIPH_ID_OWR, - - /* 72 */ - PERIPH_ID_AFI, - PERIPH_ID_CORESIGHT, - PERIPH_ID_RESERVED74, - PERIPH_ID_AVPUCQ, - PERIPH_ID_RESERVED76, - PERIPH_ID_RESERVED77, - PERIPH_ID_RESERVED78, - PERIPH_ID_RESERVED79, - - /* 80 */ - PERIPH_ID_RESERVED80, - PERIPH_ID_RESERVED81, - PERIPH_ID_RESERVED82, - PERIPH_ID_RESERVED83, - PERIPH_ID_IRAMA, - PERIPH_ID_IRAMB, - PERIPH_ID_IRAMC, - PERIPH_ID_IRAMD, - - /* 88 */ - PERIPH_ID_CRAM2, - - PERIPH_ID_COUNT, - PERIPH_ID_NONE = -1, -}; - -/* Converts a clock number to a clock register: 0=L, 1=H, 2=U */ -#define PERIPH_REG(id) ((id) >> 5) - -/* Mask value for a clock (within PERIPH_REG(id)) */ -#define PERIPH_MASK(id) (1 << ((id) & 0x1f)) - -/* return 1 if a PLL ID is in range, and not a simple PLL */ -#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && \ - (id) < CLOCK_ID_FIRST_SIMPLE) - -/* PLL stabilization delay in usec */ -#define CLOCK_PLL_STABLE_DELAY_US 300 - -/* return the current oscillator clock frequency */ -enum clock_osc_freq clock_get_osc_freq(void); - -/** - * Start PLL using the provided configuration parameters. - * - * @param id clock id - * @param divm input divider - * @param divn feedback divider - * @param divp post divider 2^n - * @param cpcon charge pump setup control - * @param lfcon loop filter setup control - * - * @returns monotonic time in us that the PLL will be stable - */ -unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn, - u32 divp, u32 cpcon, u32 lfcon); - -/** - * Read low-level parameters of a PLL. - * - * @param id clock id to read (note: USB is not supported) - * @param divm returns input divider - * @param divn returns feedback divider - * @param divp returns post divider 2^n - * @param cpcon returns charge pump setup control - * @param lfcon returns loop filter setup control - * - * @returns 0 if ok, -1 on error (invalid clock id) - */ -int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, - u32 *divp, u32 *cpcon, u32 *lfcon); - -/* - * Enable a clock - * - * @param id clock id - */ -void clock_enable(enum periph_id clkid); - -/* - * Disable a clock - * - * @param id clock id - */ -void clock_disable(enum periph_id clkid); - -/* - * Set whether a clock is enabled or disabled. - * - * @param id clock id - * @param enable 1 to enable, 0 to disable - */ -void clock_set_enable(enum periph_id clkid, int enable); - -/** - * Reset a peripheral. This puts it in reset, waits for a delay, then takes - * it out of reset and waits for th delay again. - * - * @param periph_id peripheral to reset - * @param us_delay time to delay in microseconds - */ -void reset_periph(enum periph_id periph_id, int us_delay); - -/** - * Put a peripheral into or out of reset. - * - * @param periph_id peripheral to reset - * @param enable 1 to put into reset, 0 to take out of reset - */ -void reset_set_enable(enum periph_id periph_id, int enable); - - -/* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */ -enum crc_reset_id { - /* Things we can hold in reset for each CPU */ - crc_rst_cpu = 1, - crc_rst_de = 1 << 2, /* What is de? */ - crc_rst_watchdog = 1 << 3, - crc_rst_debug = 1 << 4, -}; - -/** - * Put parts of the CPU complex into or out of reset.\ - * - * @param cpu cpu number (0 or 1 on Tegra2) - * @param which which parts of the complex to affect (OR of crc_reset_id) - * @param reset 1 to assert reset, 0 to de-assert - */ -void reset_cmplx_set_enable(int cpu, int which, int reset); - -/** - * Set the source for a peripheral clock. This plus the divisor sets the - * clock rate. You need to look up the datasheet to see the meaning of the - * source parameter as it changes for each peripheral. - * - * Warning: This function is only for use pre-relocation. Please use - * clock_start_periph_pll() instead. - * - * @param periph_id peripheral to adjust - * @param source source clock (0, 1, 2 or 3) - */ -void clock_ll_set_source(enum periph_id periph_id, unsigned source); - -/** - * Set the source and divisor for a peripheral clock. This sets the - * clock rate. You need to look up the datasheet to see the meaning of the - * source parameter as it changes for each peripheral. - * - * Warning: This function is only for use pre-relocation. Please use - * clock_start_periph_pll() instead. - * - * @param periph_id peripheral to adjust - * @param source source clock (0, 1, 2 or 3) - * @param divisor divisor value to use - */ -void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source, - unsigned divisor); - -/** - * Start a peripheral PLL clock at the given rate. This also resets the - * peripheral. - * - * @param periph_id peripheral to start - * @param parent PLL id of required parent clock - * @param rate Required clock rate in Hz - * @return rate selected in Hz, or -1U if something went wrong - */ -unsigned clock_start_periph_pll(enum periph_id periph_id, - enum clock_id parent, unsigned rate); - -/** - * Returns the rate of a peripheral clock in Hz. Since the caller almost - * certainly knows the parent clock (having just set it) we require that - * this be passed in so we don't need to work it out. - * - * @param periph_id peripheral to start - * @param parent PLL id of parent clock (used to calculate rate, you - * must know this!) - * @return clock rate of peripheral in Hz - */ -unsigned long clock_get_periph_rate(enum periph_id periph_id, - enum clock_id parent); - -/** - * Adjust peripheral PLL clock to the given rate. This does not reset the - * peripheral. If a second stage divisor is not available, pass NULL for - * extra_div. If it is available, then this parameter will return the - * divisor selected (which will be a power of 2 from 1 to 256). - * - * @param periph_id peripheral to start - * @param parent PLL id of required parent clock - * @param rate Required clock rate in Hz - * @param extra_div value for the second-stage divisor (NULL if one is - not available) - * @return rate selected in Hz, or -1U if something went wrong - */ -unsigned clock_adjust_periph_pll_div(enum periph_id periph_id, - enum clock_id parent, unsigned rate, int *extra_div); - -/** - * Returns the clock rate of a specified clock, in Hz. - * - * @param parent PLL id of clock to check - * @return rate of clock in Hz - */ -unsigned clock_get_rate(enum clock_id clkid); - -/** - * Start up a UART using low-level calls - * - * Prior to relocation clock_start_periph_pll() cannot be called. This - * function provides a way to set up a UART using low-level calls which - * do not require BSS. - * - * @param periph_id Peripheral ID of UART to enable (e,g, PERIPH_ID_UART1) - */ -void clock_ll_start_uart(enum periph_id periph_id); - -/** - * Decode a peripheral ID from a device tree node. - * - * This works by looking up the peripheral's 'clocks' node and reading out - * the second cell, which is the clock number / peripheral ID. - * - * @param blob FDT blob to use - * @param node Node to look at - * @return peripheral ID, or PERIPH_ID_NONE if none - */ -enum periph_id clock_decode_periph_id(const void *blob, int node); - -/** - * Checks if the oscillator bypass is enabled (XOBP bit) - * - * @return 1 if bypass is enabled, 0 if not - */ -int clock_get_osc_bypass(void); - -/* - * Checks that clocks are valid and prints a warning if not - * - * @return 0 if ok, -1 on error - */ -int clock_verify(void); - -/* Initialize the clocks */ -void clock_init(void); - -/* Initialize the PLLs */ -void clock_early_init(void); - -#endif diff --git a/arch/arm/include/asm/arch-tegra2/emc.h b/arch/arm/include/asm/arch-tegra2/emc.h deleted file mode 100644 index deb3d36ed2..0000000000 --- a/arch/arm/include/asm/arch-tegra2/emc.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ARCH_EMC_H_ -#define _ARCH_EMC_H_ - -#include <asm/types.h> - -#define TEGRA_EMC_NUM_REGS 46 - -/* EMC Registers */ -struct emc_ctlr { - u32 cfg; /* 0x00: EMC_CFG */ - u32 reserved0[3]; /* 0x04 ~ 0x0C */ - u32 adr_cfg; /* 0x10: EMC_ADR_CFG */ - u32 adr_cfg1; /* 0x14: EMC_ADR_CFG_1 */ - u32 reserved1[2]; /* 0x18 ~ 0x18 */ - u32 refresh_ctrl; /* 0x20: EMC_REFCTRL */ - u32 pin; /* 0x24: EMC_PIN */ - u32 timing_ctrl; /* 0x28: EMC_TIMING_CONTROL */ - u32 rc; /* 0x2C: EMC_RC */ - u32 rfc; /* 0x30: EMC_RFC */ - u32 ras; /* 0x34: EMC_RAS */ - u32 rp; /* 0x38: EMC_RP */ - u32 r2w; /* 0x3C: EMC_R2W */ - u32 w2r; /* 0x40: EMC_W2R */ - u32 r2p; /* 0x44: EMC_R2P */ - u32 w2p; /* 0x48: EMC_W2P */ - u32 rd_rcd; /* 0x4C: EMC_RD_RCD */ - u32 wd_rcd; /* 0x50: EMC_WD_RCD */ - u32 rrd; /* 0x54: EMC_RRD */ - u32 rext; /* 0x58: EMC_REXT */ - u32 wdv; /* 0x5C: EMC_WDV */ - u32 quse; /* 0x60: EMC_QUSE */ - u32 qrst; /* 0x64: EMC_QRST */ - u32 qsafe; /* 0x68: EMC_QSAFE */ - u32 rdv; /* 0x6C: EMC_RDV */ - u32 refresh; /* 0x70: EMC_REFRESH */ - u32 burst_refresh_num; /* 0x74: EMC_BURST_REFRESH_NUM */ - u32 pdex2wr; /* 0x78: EMC_PDEX2WR */ - u32 pdex2rd; /* 0x7c: EMC_PDEX2RD */ - u32 pchg2pden; /* 0x80: EMC_PCHG2PDEN */ - u32 act2pden; /* 0x84: EMC_ACT2PDEN */ - u32 ar2pden; /* 0x88: EMC_AR2PDEN */ - u32 rw2pden; /* 0x8C: EMC_RW2PDEN */ - u32 txsr; /* 0x90: EMC_TXSR */ - u32 tcke; /* 0x94: EMC_TCKE */ - u32 tfaw; /* 0x98: EMC_TFAW */ - u32 trpab; /* 0x9C: EMC_TRPAB */ - u32 tclkstable; /* 0xA0: EMC_TCLKSTABLE */ - u32 tclkstop; /* 0xA4: EMC_TCLKSTOP */ - u32 trefbw; /* 0xA8: EMC_TREFBW */ - u32 quse_extra; /* 0xAC: EMC_QUSE_EXTRA */ - u32 odt_write; /* 0xB0: EMC_ODT_WRITE */ - u32 odt_read; /* 0xB4: EMC_ODT_READ */ - u32 reserved2[5]; /* 0xB8 ~ 0xC8 */ - u32 mrs; /* 0xCC: EMC_MRS */ - u32 emrs; /* 0xD0: EMC_EMRS */ - u32 ref; /* 0xD4: EMC_REF */ - u32 pre; /* 0xD8: EMC_PRE */ - u32 nop; /* 0xDC: EMC_NOP */ - u32 self_ref; /* 0xE0: EMC_SELF_REF */ - u32 dpd; /* 0xE4: EMC_DPD */ - u32 mrw; /* 0xE8: EMC_MRW */ - u32 mrr; /* 0xEC: EMC_MRR */ - u32 reserved3; /* 0xF0: */ - u32 fbio_cfg1; /* 0xF4: EMC_FBIO_CFG1 */ - u32 fbio_dqsib_dly; /* 0xF8: EMC_FBIO_DQSIB_DLY */ - u32 fbio_dqsib_dly_msb; /* 0xFC: EMC_FBIO_DQSIB_DLY_MSG */ - u32 fbio_spare; /* 0x100: SBIO_SPARE */ - /* There are more registers ... */ -}; - -/** - * Set up the EMC for the given rate. The timing parameters are retrieved - * from the device tree "nvidia,tegra20-emc" node and its - * "nvidia,tegra20-emc-table" sub-nodes. - * - * @param blob Device tree blob - * @param rate Clock speed of memory controller in Hz (=2x memory bus rate) - * @return 0 if ok, else -ve error code (look in emc.c to decode it) - */ -int tegra_set_emc(const void *blob, unsigned rate); - -/** - * Get a pointer to the EMC controller from the device tree. - * - * @param blob Device tree blob - * @return pointer to EMC controller - */ -struct emc_ctlr *emc_get_controller(const void *blob); - -#endif diff --git a/arch/arm/include/asm/arch-tegra2/flow.h b/arch/arm/include/asm/arch-tegra2/flow.h deleted file mode 100644 index cce6cbf7d0..0000000000 --- a/arch/arm/include/asm/arch-tegra2/flow.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2010, 2011 - * NVIDIA Corporation <www.nvidia.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _FLOW_H_ -#define _FLOW_H_ - -struct flow_ctlr { - u32 halt_cpu_events; - u32 halt_cop_events; - u32 cpu_csr; - u32 cop_csr; - u32 halt_cpu1_events; - u32 cpu1_csr; -}; - -#endif diff --git a/arch/arm/include/asm/arch-tegra2/funcmux.h b/arch/arm/include/asm/arch-tegra2/funcmux.h deleted file mode 100644 index dcd512f084..0000000000 --- a/arch/arm/include/asm/arch-tegra2/funcmux.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* Tegra2 high-level function multiplexing */ - -#ifndef __FUNCMUX_H -#define __FUNCMUX_H - -/* Configs supported by the func mux */ -enum { - FUNCMUX_DEFAULT = 0, /* default config */ - - /* UART configs */ - FUNCMUX_UART1_IRRX_IRTX = 0, - FUNCMUX_UART1_UAA_UAB, - FUNCMUX_UART1_GPU, - FUNCMUX_UART1_SDIO1, - FUNCMUX_UART2_IRDA = 0, - FUNCMUX_UART4_GMC = 0, - - /* I2C configs */ - FUNCMUX_DVC_I2CP = 0, - FUNCMUX_I2C1_RM = 0, - FUNCMUX_I2C2_DDC = 0, - FUNCMUX_I2C2_PTA, - FUNCMUX_I2C3_DTF = 0, - - /* SDMMC configs */ - FUNCMUX_SDMMC1_SDIO1_4BIT = 0, - FUNCMUX_SDMMC2_DTA_DTD_8BIT = 0, - FUNCMUX_SDMMC3_SDB_4BIT = 0, - FUNCMUX_SDMMC3_SDB_SLXA_8BIT, - FUNCMUX_SDMMC4_ATC_ATD_8BIT = 0, - FUNCMUX_SDMMC4_ATB_GMA_4_BIT, - FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT, - - /* USB configs */ - FUNCMUX_USB2_ULPI = 0, - - /* Serial Flash configs */ - FUNCMUX_SPI1_GMC_GMD = 0, -}; - -/** - * Select a config for a particular peripheral. - * - * Each peripheral can operate through a number of configurations, - * which are sets of pins that it uses to bring out its signals. - * The basic config is 0, and higher numbers indicate different - * pinmux settings to bring the peripheral out on other pins, - * - * This function also disables tristate for the function's pins, - * so that they operate in normal mode. - * - * @param id Peripheral id - * @param config Configuration to use (FUNCMUX_...), 0 for default - * @return 0 if ok, -1 on error (e.g. incorrect id or config) - */ -int funcmux_select(enum periph_id id, int config); - -#endif diff --git a/arch/arm/include/asm/arch-tegra2/fuse.h b/arch/arm/include/asm/arch-tegra2/fuse.h deleted file mode 100644 index b7e3808a4f..0000000000 --- a/arch/arm/include/asm/arch-tegra2/fuse.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _FUSE_H_ -#define _FUSE_H_ - -/* FUSE registers */ -struct fuse_regs { - u32 reserved0[64]; /* 0x00 - 0xFC: */ - u32 production_mode; /* 0x100: FUSE_PRODUCTION_MODE */ - u32 reserved1[3]; /* 0x104 - 0x10c: */ - u32 sku_info; /* 0x110 */ - u32 reserved2[13]; /* 0x114 - 0x144: */ - u32 fa; /* 0x148: FUSE_FA */ - u32 reserved3[21]; /* 0x14C - 0x19C: */ - u32 security_mode; /* 0x1A0: FUSE_SECURITY_MODE */ -}; - -#endif /* ifndef _FUSE_H_ */ diff --git a/arch/arm/include/asm/arch-tegra2/gp_padctrl.h b/arch/arm/include/asm/arch-tegra2/gp_padctrl.h deleted file mode 100644 index 1755ab2eaa..0000000000 --- a/arch/arm/include/asm/arch-tegra2/gp_padctrl.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _GP_PADCTRL_H_ -#define _GP_PADCTRL_H_ - -/* APB_MISC_GP and padctrl registers */ -struct apb_misc_gp_ctlr { - u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ - u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ - u32 reserved0[22]; /* 0x08 - 0x5C: */ - u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ - u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ - u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ - u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */ - u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ - u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ - u32 cdevcfg1; /* 0x78: APB_MISC_GP_CDEV1CFGPADCTRL */ - u32 cdevcfg2; /* 0x7C: APB_MISC_GP_CDEV2CFGPADCTRL */ - u32 csuscfg; /* 0x80: APB_MISC_GP_CSUSCFGPADCTRL */ - u32 dap1cfg; /* 0x84: APB_MISC_GP_DAP1CFGPADCTRL */ - u32 dap2cfg; /* 0x88: APB_MISC_GP_DAP2CFGPADCTRL */ - u32 dap3cfg; /* 0x8C: APB_MISC_GP_DAP3CFGPADCTRL */ - u32 dap4cfg; /* 0x90: APB_MISC_GP_DAP4CFGPADCTRL */ - u32 dbgcfg; /* 0x94: APB_MISC_GP_DBGCFGPADCTRL */ - u32 lcdcfg1; /* 0x98: APB_MISC_GP_LCDCFG1PADCTRL */ - u32 lcdcfg2; /* 0x9C: APB_MISC_GP_LCDCFG2PADCTRL */ - u32 sdmmc2_cfg; /* 0xA0: APB_MISC_GP_SDMMC2CFGPADCTRL */ - u32 sdmmc3_cfg; /* 0xA4: APB_MISC_GP_SDMMC3CFGPADCTRL */ - u32 spicfg; /* 0xA8: APB_MISC_GP_SPICFGPADCTRL */ - u32 uaacfg; /* 0xAC: APB_MISC_GP_UAACFGPADCTRL */ - u32 uabcfg; /* 0xB0: APB_MISC_GP_UABCFGPADCTRL */ - u32 uart2cfg; /* 0xB4: APB_MISC_GP_UART2CFGPADCTRL */ - u32 uart3cfg; /* 0xB8: APB_MISC_GP_UART3CFGPADCTRL */ - u32 vicfg1; /* 0xBC: APB_MISC_GP_VICFG1PADCTRL */ - u32 vicfg2; /* 0xC0: APB_MISC_GP_VICFG2PADCTRL */ - u32 xm2cfga; /* 0xC4: APB_MISC_GP_XM2CFGAPADCTRL */ - u32 xm2cfgc; /* 0xC8: APB_MISC_GP_XM2CFGCPADCTRL */ - u32 xm2cfgd; /* 0xCC: APB_MISC_GP_XM2CFGDPADCTRL */ - u32 xm2clkcfg; /* 0xD0: APB_MISC_GP_XM2CLKCFGPADCTRL */ - u32 memcomp; /* 0xD4: APB_MISC_GP_MEMCOMPPADCTRL */ -}; - -/* bit fields definitions for APB_MISC_GP_HIDREV register */ -#define HIDREV_CHIPID_SHIFT 8 -#define HIDREV_CHIPID_MASK (0xff << HIDREV_CHIPID_SHIFT) -#define HIDREV_MAJORPREV_SHIFT 4 -#define HIDREV_MAJORPREV_MASK (0xf << HIDREV_MAJORPREV_SHIFT) - -/* CHIPID field returned from APB_MISC_GP_HIDREV register */ -#define CHIPID_TEGRA2 0x20 - -#endif diff --git a/arch/arm/include/asm/arch-tegra2/gpio.h b/arch/arm/include/asm/arch-tegra2/gpio.h deleted file mode 100644 index 40ddb02565..0000000000 --- a/arch/arm/include/asm/arch-tegra2/gpio.h +++ /dev/null @@ -1,290 +0,0 @@ -/* - * Copyright (c) 2011, Google Inc. All rights reserved. - * See file CREDITS for list of people who contributed to this - * project. - * Portions Copyright 2011-2012 NVIDIA Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _TEGRA_GPIO_H_ -#define _TEGRA_GPIO_H_ - -/* - * The Tegra 2x GPIO controller has 224 GPIOs arranged in 7 banks of 4 ports, - * each with 8 GPIOs. - */ -#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ -#define TEGRA_GPIO_BANKS 7 /* number of banks */ -#define MAX_NUM_GPIOS (TEGRA_GPIO_PORTS * TEGRA_GPIO_BANKS * 8) -#define GPIO_NAME_SIZE 20 /* gpio_request max label len */ - -/* GPIO Controller registers for a single bank */ -struct gpio_ctlr_bank { - uint gpio_config[TEGRA_GPIO_PORTS]; - uint gpio_dir_out[TEGRA_GPIO_PORTS]; - uint gpio_out[TEGRA_GPIO_PORTS]; - uint gpio_in[TEGRA_GPIO_PORTS]; - uint gpio_int_status[TEGRA_GPIO_PORTS]; - uint gpio_int_enable[TEGRA_GPIO_PORTS]; - uint gpio_int_level[TEGRA_GPIO_PORTS]; - uint gpio_int_clear[TEGRA_GPIO_PORTS]; -}; - -struct gpio_ctlr { - struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; -}; - -#define GPIO_BANK(x) ((x) >> 5) -#define GPIO_PORT(x) (((x) >> 3) & 0x3) -#define GPIO_FULLPORT(x) ((x) >> 3) -#define GPIO_BIT(x) ((x) & 0x7) - -enum gpio_pin { - GPIO_PA0 = 0, /* pin 0 */ - GPIO_PA1, - GPIO_PA2, - GPIO_PA3, - GPIO_PA4, - GPIO_PA5, - GPIO_PA6, - GPIO_PA7, - GPIO_PB0, /* pin 8 */ - GPIO_PB1, - GPIO_PB2, - GPIO_PB3, - GPIO_PB4, - GPIO_PB5, - GPIO_PB6, - GPIO_PB7, - GPIO_PC0, /* pin 16 */ - GPIO_PC1, - GPIO_PC2, - GPIO_PC3, - GPIO_PC4, - GPIO_PC5, - GPIO_PC6, - GPIO_PC7, - GPIO_PD0, /* pin 24 */ - GPIO_PD1, - GPIO_PD2, - GPIO_PD3, - GPIO_PD4, - GPIO_PD5, - GPIO_PD6, - GPIO_PD7, - GPIO_PE0, /* pin 32 */ - GPIO_PE1, - GPIO_PE2, - GPIO_PE3, - GPIO_PE4, - GPIO_PE5, - GPIO_PE6, - GPIO_PE7, - GPIO_PF0, /* pin 40 */ - GPIO_PF1, - GPIO_PF2, - GPIO_PF3, - GPIO_PF4, - GPIO_PF5, - GPIO_PF6, - GPIO_PF7, - GPIO_PG0, /* pin 48 */ - GPIO_PG1, - GPIO_PG2, - GPIO_PG3, - GPIO_PG4, - GPIO_PG5, - GPIO_PG6, - GPIO_PG7, - GPIO_PH0, /* pin 56 */ - GPIO_PH1, - GPIO_PH2, - GPIO_PH3, - GPIO_PH4, - GPIO_PH5, - GPIO_PH6, - GPIO_PH7, - GPIO_PI0, /* pin 64 */ - GPIO_PI1, - GPIO_PI2, - GPIO_PI3, - GPIO_PI4, - GPIO_PI5, - GPIO_PI6, - GPIO_PI7, - GPIO_PJ0, /* pin 72 */ - GPIO_PJ1, - GPIO_PJ2, - GPIO_PJ3, - GPIO_PJ4, - GPIO_PJ5, - GPIO_PJ6, - GPIO_PJ7, - GPIO_PK0, /* pin 80 */ - GPIO_PK1, - GPIO_PK2, - GPIO_PK3, - GPIO_PK4, - GPIO_PK5, - GPIO_PK6, - GPIO_PK7, - GPIO_PL0, /* pin 88 */ - GPIO_PL1, - GPIO_PL2, - GPIO_PL3, - GPIO_PL4, - GPIO_PL5, - GPIO_PL6, - GPIO_PL7, - GPIO_PM0, /* pin 96 */ - GPIO_PM1, - GPIO_PM2, - GPIO_PM3, - GPIO_PM4, - GPIO_PM5, - GPIO_PM6, - GPIO_PM7, - GPIO_PN0, /* pin 104 */ - GPIO_PN1, - GPIO_PN2, - GPIO_PN3, - GPIO_PN4, - GPIO_PN5, - GPIO_PN6, - GPIO_PN7, - GPIO_PO0, /* pin 112 */ - GPIO_PO1, - GPIO_PO2, - GPIO_PO3, - GPIO_PO4, - GPIO_PO5, - GPIO_PO6, - GPIO_PO7, - GPIO_PP0, /* pin 120 */ - GPIO_PP1, - GPIO_PP2, - GPIO_PP3, - GPIO_PP4, - GPIO_PP5, - GPIO_PP6, - GPIO_PP7, - GPIO_PQ0, /* pin 128 */ - GPIO_PQ1, - GPIO_PQ2, - GPIO_PQ3, - GPIO_PQ4, - GPIO_PQ5, - GPIO_PQ6, - GPIO_PQ7, - GPIO_PR0, /* pin 136 */ - GPIO_PR1, - GPIO_PR2, - GPIO_PR3, - GPIO_PR4, - GPIO_PR5, - GPIO_PR6, - GPIO_PR7, - GPIO_PS0, /* pin 144 */ - GPIO_PS1, - GPIO_PS2, - GPIO_PS3, - GPIO_PS4, - GPIO_PS5, - GPIO_PS6, - GPIO_PS7, - GPIO_PT0, /* pin 152 */ - GPIO_PT1, - GPIO_PT2, - GPIO_PT3, - GPIO_PT4, - GPIO_PT5, - GPIO_PT6, - GPIO_PT7, - GPIO_PU0, /* pin 160 */ - GPIO_PU1, - GPIO_PU2, - GPIO_PU3, - GPIO_PU4, - GPIO_PU5, - GPIO_PU6, - GPIO_PU7, - GPIO_PV0, /* pin 168 */ - GPIO_PV1, - GPIO_PV2, - GPIO_PV3, - GPIO_PV4, - GPIO_PV5, - GPIO_PV6, - GPIO_PV7, - GPIO_PW0, /* pin 176 */ - GPIO_PW1, - GPIO_PW2, - GPIO_PW3, - GPIO_PW4, - GPIO_PW5, - GPIO_PW6, - GPIO_PW7, - GPIO_PX0, /* pin 184 */ - GPIO_PX1, - GPIO_PX2, - GPIO_PX3, - GPIO_PX4, - GPIO_PX5, - GPIO_PX6, - GPIO_PX7, - GPIO_PY0, /* pin 192 */ - GPIO_PY1, - GPIO_PY2, - GPIO_PY3, - GPIO_PY4, - GPIO_PY5, - GPIO_PY6, - GPIO_PY7, - GPIO_PZ0, /* pin 200 */ - GPIO_PZ1, - GPIO_PZ2, - GPIO_PZ3, - GPIO_PZ4, - GPIO_PZ5, - GPIO_PZ6, - GPIO_PZ7, - GPIO_PAA0, /* pin 208 */ - GPIO_PAA1, - GPIO_PAA2, - GPIO_PAA3, - GPIO_PAA4, - GPIO_PAA5, - GPIO_PAA6, - GPIO_PAA7, - GPIO_PBB0, /* pin 216 */ - GPIO_PBB1, - GPIO_PBB2, - GPIO_PBB3, - GPIO_PBB4, - GPIO_PBB5, - GPIO_PBB6, - GPIO_PBB7, /* pin 223 */ -}; - -/* - * Tegra2-specific GPIO API - */ - -void gpio_info(void); - -#define gpio_status() gpio_info() -#endif /* TEGRA_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-tegra2/mmc.h b/arch/arm/include/asm/arch-tegra2/mmc.h deleted file mode 100644 index c1f12dbe49..0000000000 --- a/arch/arm/include/asm/arch-tegra2/mmc.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2011, Google Inc. All rights reserved. - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _TEGRA2_MMC_H_ -#define _TEGRA2_MMC_H_ - -int tegra2_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio); - -#endif /* TEGRA2_MMC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra2/pinmux.h b/arch/arm/include/asm/arch-tegra2/pinmux.h deleted file mode 100644 index 03fa7ca643..0000000000 --- a/arch/arm/include/asm/arch-tegra2/pinmux.h +++ /dev/null @@ -1,354 +0,0 @@ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _PINMUX_H_ -#define _PINMUX_H_ - -/* - * Pin groups which we adjust. There are three basic attributes of each pin - * group which use this enum: - * - * - function - * - pullup / pulldown - * - tristate or normal - */ -enum pmux_pingrp { - /* APB_MISC_PP_TRISTATE_REG_A_0 */ - PINGRP_ATA, - PINGRP_ATB, - PINGRP_ATC, - PINGRP_ATD, - PINGRP_CDEV1, - PINGRP_CDEV2, - PINGRP_CSUS, - PINGRP_DAP1, - - PINGRP_DAP2, - PINGRP_DAP3, - PINGRP_DAP4, - PINGRP_DTA, - PINGRP_DTB, - PINGRP_DTC, - PINGRP_DTD, - PINGRP_DTE, - - PINGRP_GPU, - PINGRP_GPV, - PINGRP_I2CP, - PINGRP_IRTX, - PINGRP_IRRX, - PINGRP_KBCB, - PINGRP_KBCA, - PINGRP_PMC, - - PINGRP_PTA, - PINGRP_RM, - PINGRP_KBCE, - PINGRP_KBCF, - PINGRP_GMA, - PINGRP_GMC, - PINGRP_SDIO1, - PINGRP_OWC, - - /* 32: APB_MISC_PP_TRISTATE_REG_B_0 */ - PINGRP_GME, - PINGRP_SDC, - PINGRP_SDD, - PINGRP_RESERVED0, - PINGRP_SLXA, - PINGRP_SLXC, - PINGRP_SLXD, - PINGRP_SLXK, - - PINGRP_SPDI, - PINGRP_SPDO, - PINGRP_SPIA, - PINGRP_SPIB, - PINGRP_SPIC, - PINGRP_SPID, - PINGRP_SPIE, - PINGRP_SPIF, - - PINGRP_SPIG, - PINGRP_SPIH, - PINGRP_UAA, - PINGRP_UAB, - PINGRP_UAC, - PINGRP_UAD, - PINGRP_UCA, - PINGRP_UCB, - - PINGRP_RESERVED1, - PINGRP_ATE, - PINGRP_KBCC, - PINGRP_RESERVED2, - PINGRP_RESERVED3, - PINGRP_GMB, - PINGRP_GMD, - PINGRP_DDC, - - /* 64: APB_MISC_PP_TRISTATE_REG_C_0 */ - PINGRP_LD0, - PINGRP_LD1, - PINGRP_LD2, - PINGRP_LD3, - PINGRP_LD4, - PINGRP_LD5, - PINGRP_LD6, - PINGRP_LD7, - - PINGRP_LD8, - PINGRP_LD9, - PINGRP_LD10, - PINGRP_LD11, - PINGRP_LD12, - PINGRP_LD13, - PINGRP_LD14, - PINGRP_LD15, - - PINGRP_LD16, - PINGRP_LD17, - PINGRP_LHP0, - PINGRP_LHP1, - PINGRP_LHP2, - PINGRP_LVP0, - PINGRP_LVP1, - PINGRP_HDINT, - - PINGRP_LM0, - PINGRP_LM1, - PINGRP_LVS, - PINGRP_LSC0, - PINGRP_LSC1, - PINGRP_LSCK, - PINGRP_LDC, - PINGRP_LCSN, - - /* 96: APB_MISC_PP_TRISTATE_REG_D_0 */ - PINGRP_LSPI, - PINGRP_LSDA, - PINGRP_LSDI, - PINGRP_LPW0, - PINGRP_LPW1, - PINGRP_LPW2, - PINGRP_LDI, - PINGRP_LHS, - - PINGRP_LPP, - PINGRP_RESERVED4, - PINGRP_KBCD, - PINGRP_GPU7, - PINGRP_DTF, - PINGRP_UDA, - PINGRP_CRTP, - PINGRP_SDB, - - /* these pin groups only have pullup and pull down control */ - PINGRP_FIRST_NO_MUX, - PINGRP_CK32 = PINGRP_FIRST_NO_MUX, - PINGRP_DDRC, - PINGRP_PMCA, - PINGRP_PMCB, - PINGRP_PMCC, - PINGRP_PMCD, - PINGRP_PMCE, - PINGRP_XM2C, - PINGRP_XM2D, - - PINGRP_COUNT, -}; - -/* - * Functions which can be assigned to each of the pin groups. The values here - * bear no relation to the values programmed into pinmux registers and are - * purely a convenience. The translation is done through a table search. - */ -enum pmux_func { - PMUX_FUNC_AHB_CLK, - PMUX_FUNC_APB_CLK, - PMUX_FUNC_AUDIO_SYNC, - PMUX_FUNC_CRT, - PMUX_FUNC_DAP1, - PMUX_FUNC_DAP2, - PMUX_FUNC_DAP3, - PMUX_FUNC_DAP4, - PMUX_FUNC_DAP5, - PMUX_FUNC_DISPA, - PMUX_FUNC_DISPB, - PMUX_FUNC_EMC_TEST0_DLL, - PMUX_FUNC_EMC_TEST1_DLL, - PMUX_FUNC_GMI, - PMUX_FUNC_GMI_INT, - PMUX_FUNC_HDMI, - PMUX_FUNC_I2C, - PMUX_FUNC_I2C2, - PMUX_FUNC_I2C3, - PMUX_FUNC_IDE, - PMUX_FUNC_IRDA, - PMUX_FUNC_KBC, - PMUX_FUNC_MIO, - PMUX_FUNC_MIPI_HS, - PMUX_FUNC_NAND, - PMUX_FUNC_OSC, - PMUX_FUNC_OWR, - PMUX_FUNC_PCIE, - PMUX_FUNC_PLLA_OUT, - PMUX_FUNC_PLLC_OUT1, - PMUX_FUNC_PLLM_OUT1, - PMUX_FUNC_PLLP_OUT2, - PMUX_FUNC_PLLP_OUT3, - PMUX_FUNC_PLLP_OUT4, - PMUX_FUNC_PWM, - PMUX_FUNC_PWR_INTR, - PMUX_FUNC_PWR_ON, - PMUX_FUNC_RTCK, - PMUX_FUNC_SDIO1, - PMUX_FUNC_SDIO2, - PMUX_FUNC_SDIO3, - PMUX_FUNC_SDIO4, - PMUX_FUNC_SFLASH, - PMUX_FUNC_SPDIF, - PMUX_FUNC_SPI1, - PMUX_FUNC_SPI2, - PMUX_FUNC_SPI2_ALT, - PMUX_FUNC_SPI3, - PMUX_FUNC_SPI4, - PMUX_FUNC_TRACE, - PMUX_FUNC_TWC, - PMUX_FUNC_UARTA, - PMUX_FUNC_UARTB, - PMUX_FUNC_UARTC, - PMUX_FUNC_UARTD, - PMUX_FUNC_UARTE, - PMUX_FUNC_ULPI, - PMUX_FUNC_VI, - PMUX_FUNC_VI_SENSOR_CLK, - PMUX_FUNC_XIO, - PMUX_FUNC_SAFE, - - /* These don't have a name, but can be used in the table */ - PMUX_FUNC_RSVD1, - PMUX_FUNC_RSVD2, - PMUX_FUNC_RSVD3, - PMUX_FUNC_RSVD4, - PMUX_FUNC_RSVD, /* Not valid and should not be used */ - - PMUX_FUNC_COUNT, - - PMUX_FUNC_NONE = -1, -}; - -/* return 1 if a pmux_func is in range */ -#define pmux_func_isvalid(func) ((func) >= 0 && (func) < PMUX_FUNC_COUNT && \ - (func) != PMUX_FUNC_RSVD) - -/* The pullup/pulldown state of a pin group */ -enum pmux_pull { - PMUX_PULL_NORMAL = 0, - PMUX_PULL_DOWN, - PMUX_PULL_UP, -}; - -/* Defines whether a pin group is tristated or in normal operation */ -enum pmux_tristate { - PMUX_TRI_NORMAL = 0, - PMUX_TRI_TRISTATE = 1, -}; - -/* Available power domains used by pin groups */ -enum pmux_vddio { - PMUX_VDDIO_BB = 0, - PMUX_VDDIO_LCD, - PMUX_VDDIO_VI, - PMUX_VDDIO_UART, - PMUX_VDDIO_DDR, - PMUX_VDDIO_NAND, - PMUX_VDDIO_SYS, - PMUX_VDDIO_AUDIO, - PMUX_VDDIO_SD, - - PMUX_VDDIO_NONE -}; - -enum { - PMUX_TRISTATE_REGS = 4, - PMUX_MUX_REGS = 7, - PMUX_PULL_REGS = 5, -}; - -/* APB MISC Pin Mux and Tristate (APB_MISC_PP_) registers */ -struct pmux_tri_ctlr { - uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */ - uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */ - uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */ - uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */ - uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */ - uint pmt_tri[PMUX_TRISTATE_REGS];/* _TRI_STATE_REG_A/B/C/D_0 14-20 */ - uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */ - - uint pmt_reserved[22]; /* ABP_MISC_PP_ reserved offs 28-7C */ - - uint pmt_ctl[PMUX_MUX_REGS]; /* _PIN_MUX_CTL_A-G_0, offset 80 */ - uint pmt_reserved4; /* ABP_MISC_PP_ reserved offset 9c */ - uint pmt_pull[PMUX_PULL_REGS]; /* APB_MISC_PP_PULLUPDOWN_REG_A-E */ -}; - -/* - * This defines the configuration for a pin, including the function assigned, - * pull up/down settings and tristate settings. Having set up one of these - * you can call pinmux_config_pingroup() to configure a pin in one step. Also - * available is pinmux_config_table() to configure a list of pins. - */ -struct pingroup_config { - enum pmux_pingrp pingroup; /* pin group PINGRP_... */ - enum pmux_func func; /* function to assign FUNC_... */ - enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/ - enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */ -}; - -/* Set a pin group to tristate */ -void pinmux_tristate_enable(enum pmux_pingrp pin); - -/* Set a pin group to normal (non tristate) */ -void pinmux_tristate_disable(enum pmux_pingrp pin); - -/* Set the pull up/down feature for a pin group */ -void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd); - -/* Set the mux function for a pin group */ -void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func); - -/* Set the complete configuration for a pin group */ -void pinmux_config_pingroup(struct pingroup_config *config); - -void pinmux_set_tristate(enum pmux_pingrp pin, int enable); - -/** - * Configuure a list of pin groups - * - * @param config List of config items - * @param len Number of config items in list - */ -void pinmux_config_table(struct pingroup_config *config, int len); - -#endif /* PINMUX_H */ diff --git a/arch/arm/include/asm/arch-tegra2/pmc.h b/arch/arm/include/asm/arch-tegra2/pmc.h deleted file mode 100644 index b1d47cd2e3..0000000000 --- a/arch/arm/include/asm/arch-tegra2/pmc.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _PMC_H_ -#define _PMC_H_ - -/* Power Management Controller (APBDEV_PMC_) registers */ -struct pmc_ctlr { - uint pmc_cntrl; /* _CNTRL_0, offset 00 */ - uint pmc_sec_disable; /* _SEC_DISABLE_0, offset 04 */ - uint pmc_pmc_swrst; /* _PMC_SWRST_0, offset 08 */ - uint pmc_wake_mask; /* _WAKE_MASK_0, offset 0C */ - uint pmc_wake_lvl; /* _WAKE_LVL_0, offset 10 */ - uint pmc_wake_status; /* _WAKE_STATUS_0, offset 14 */ - uint pmc_sw_wake_status; /* _SW_WAKE_STATUS_0, offset 18 */ - uint pmc_dpd_pads_oride; /* _DPD_PADS_ORIDE_0, offset 1C */ - uint pmc_dpd_sample; /* _DPD_PADS_SAMPLE_0, offset 20 */ - uint pmc_dpd_enable; /* _DPD_PADS_ENABLE_0, offset 24 */ - uint pmc_pwrgate_timer_off; /* _PWRGATE_TIMER_OFF_0, offset 28 */ - uint pmc_pwrgate_timer_on; /* _PWRGATE_TIMER_ON_0, offset 2C */ - uint pmc_pwrgate_toggle; /* _PWRGATE_TOGGLE_0, offset 30 */ - uint pmc_remove_clamping; /* _REMOVE_CLAMPING_CMD_0, offset 34 */ - uint pmc_pwrgate_status; /* _PWRGATE_STATUS_0, offset 38 */ - uint pmc_pwrgood_timer; /* _PWRGOOD_TIMER_0, offset 3C */ - uint pmc_blink_timer; /* _BLINK_TIMER_0, offset 40 */ - uint pmc_no_iopower; /* _NO_IOPOWER_0, offset 44 */ - uint pmc_pwr_det; /* _PWR_DET_0, offset 48 */ - uint pmc_pwr_det_latch; /* _PWR_DET_LATCH_0, offset 4C */ - - uint pmc_scratch0; /* _SCRATCH0_0, offset 50 */ - uint pmc_scratch1; /* _SCRATCH1_0, offset 54 */ - uint pmc_scratch2; /* _SCRATCH2_0, offset 58 */ - uint pmc_scratch3; /* _SCRATCH3_0, offset 5C */ - uint pmc_scratch4; /* _SCRATCH4_0, offset 60 */ - uint pmc_scratch5; /* _SCRATCH5_0, offset 64 */ - uint pmc_scratch6; /* _SCRATCH6_0, offset 68 */ - uint pmc_scratch7; /* _SCRATCH7_0, offset 6C */ - uint pmc_scratch8; /* _SCRATCH8_0, offset 70 */ - uint pmc_scratch9; /* _SCRATCH9_0, offset 74 */ - uint pmc_scratch10; /* _SCRATCH10_0, offset 78 */ - uint pmc_scratch11; /* _SCRATCH11_0, offset 7C */ - uint pmc_scratch12; /* _SCRATCH12_0, offset 80 */ - uint pmc_scratch13; /* _SCRATCH13_0, offset 84 */ - uint pmc_scratch14; /* _SCRATCH14_0, offset 88 */ - uint pmc_scratch15; /* _SCRATCH15_0, offset 8C */ - uint pmc_scratch16; /* _SCRATCH16_0, offset 90 */ - uint pmc_scratch17; /* _SCRATCH17_0, offset 94 */ - uint pmc_scratch18; /* _SCRATCH18_0, offset 98 */ - uint pmc_scratch19; /* _SCRATCH19_0, offset 9C */ - uint pmc_scratch20; /* _SCRATCH20_0, offset A0 */ - uint pmc_scratch21; /* _SCRATCH21_0, offset A4 */ - uint pmc_scratch22; /* _SCRATCH22_0, offset A8 */ - uint pmc_scratch23; /* _SCRATCH23_0, offset AC */ - - uint pmc_secure_scratch0; /* _SECURE_SCRATCH0_0, offset B0 */ - uint pmc_secure_scratch1; /* _SECURE_SCRATCH1_0, offset B4 */ - uint pmc_secure_scratch2; /* _SECURE_SCRATCH2_0, offset B8 */ - uint pmc_secure_scratch3; /* _SECURE_SCRATCH3_0, offset BC */ - uint pmc_secure_scratch4; /* _SECURE_SCRATCH4_0, offset C0 */ - uint pmc_secure_scratch5; /* _SECURE_SCRATCH5_0, offset C4 */ - - uint pmc_cpupwrgood_timer; /* _CPUPWRGOOD_TIMER_0, offset C8 */ - uint pmc_cpupwroff_timer; /* _CPUPWROFF_TIMER_0, offset CC */ - uint pmc_pg_mask; /* _PG_MASK_0, offset D0 */ - uint pmc_pg_mask_1; /* _PG_MASK_1_0, offset D4 */ - uint pmc_auto_wake_lvl; /* _AUTO_WAKE_LVL_0, offset D8 */ - uint pmc_auto_wake_lvl_mask; /* _AUTO_WAKE_LVL_MASK_0, offset DC */ - uint pmc_wake_delay; /* _WAKE_DELAY_0, offset E0 */ - uint pmc_pwr_det_val; /* _PWR_DET_VAL_0, offset E4 */ - uint pmc_ddr_pwr; /* _DDR_PWR_0, offset E8 */ - uint pmc_usb_debounce_del; /* _USB_DEBOUNCE_DEL_0, offset EC */ - uint pmc_usb_ao; /* _USB_AO_0, offset F0 */ - uint pmc_crypto_op; /* _CRYPTO_OP__0, offset F4 */ - uint pmc_pllp_wb0_override; /* _PLLP_WB0_OVERRIDE_0, offset F8 */ - - uint pmc_scratch24; /* _SCRATCH24_0, offset FC */ - uint pmc_scratch25; /* _SCRATCH24_0, offset 100 */ - uint pmc_scratch26; /* _SCRATCH24_0, offset 104 */ - uint pmc_scratch27; /* _SCRATCH24_0, offset 108 */ - uint pmc_scratch28; /* _SCRATCH24_0, offset 10C */ - uint pmc_scratch29; /* _SCRATCH24_0, offset 110 */ - uint pmc_scratch30; /* _SCRATCH24_0, offset 114 */ - uint pmc_scratch31; /* _SCRATCH24_0, offset 118 */ - uint pmc_scratch32; /* _SCRATCH24_0, offset 11C */ - uint pmc_scratch33; /* _SCRATCH24_0, offset 120 */ - uint pmc_scratch34; /* _SCRATCH24_0, offset 124 */ - uint pmc_scratch35; /* _SCRATCH24_0, offset 128 */ - uint pmc_scratch36; /* _SCRATCH24_0, offset 12C */ - uint pmc_scratch37; /* _SCRATCH24_0, offset 130 */ - uint pmc_scratch38; /* _SCRATCH24_0, offset 134 */ - uint pmc_scratch39; /* _SCRATCH24_0, offset 138 */ - uint pmc_scratch40; /* _SCRATCH24_0, offset 13C */ - uint pmc_scratch41; /* _SCRATCH24_0, offset 140 */ - uint pmc_scratch42; /* _SCRATCH24_0, offset 144 */ - - uint pmc_bo_mirror0; /* _BOUNDOUT_MIRROR0_0, offset 148 */ - uint pmc_bo_mirror1; /* _BOUNDOUT_MIRROR1_0, offset 14C */ - uint pmc_bo_mirror2; /* _BOUNDOUT_MIRROR2_0, offset 150 */ - uint pmc_sys_33v_en; /* _SYS_33V_EN_0, offset 154 */ - uint pmc_bo_mirror_access; /* _BOUNDOUT_MIRROR_ACCESS_0, off158 */ - uint pmc_gate; /* _GATE_0, offset 15C */ -}; - -#define CPU_PWRED 1 -#define CPU_CLMP 1 - -#define PARTID_CP 0xFFFFFFF8 -#define START_CP (1 << 8) - -#define CPUPWRREQ_OE (1 << 16) - -#endif /* PMC_H */ diff --git a/arch/arm/include/asm/arch-tegra2/pmu.h b/arch/arm/include/asm/arch-tegra2/pmu.h deleted file mode 100644 index 390815fc24..0000000000 --- a/arch/arm/include/asm/arch-tegra2/pmu.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ARCH_PMU_H_ -#define _ARCH_PMU_H_ - -/* Set core and CPU voltages to nominal levels */ -int pmu_set_nominal(void); - -#endif /* _ARCH_PMU_H_ */ diff --git a/arch/arm/include/asm/arch-tegra2/scu.h b/arch/arm/include/asm/arch-tegra2/scu.h deleted file mode 100644 index 787ded0fe0..0000000000 --- a/arch/arm/include/asm/arch-tegra2/scu.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _SCU_H_ -#define _SCU_H_ - -/* ARM Snoop Control Unit (SCU) registers */ -struct scu_ctlr { - uint scu_ctrl; /* SCU Control Register, offset 00 */ - uint scu_cfg; /* SCU Config Register, offset 04 */ - uint scu_cpu_pwr_stat; /* SCU CPU Power Status Register, offset 08 */ - uint scu_inv_all; /* SCU Invalidate All Register, offset 0C */ - uint scu_reserved0[12]; /* reserved, offset 10-3C */ - uint scu_filt_start; /* SCU Filtering Start Address Reg, offset 40 */ - uint scu_filt_end; /* SCU Filtering End Address Reg, offset 44 */ - uint scu_reserved1[2]; /* reserved, offset 48-4C */ - uint scu_acc_ctl; /* SCU Access Control Register, offset 50 */ - uint scu_ns_acc_ctl; /* SCU Non-secure Access Cntrl Reg, offset 54 */ -}; - -#define SCU_CTRL_ENABLE (1 << 0) - -#endif /* SCU_H */ diff --git a/arch/arm/include/asm/arch-tegra2/sdram_param.h b/arch/arm/include/asm/arch-tegra2/sdram_param.h deleted file mode 100644 index 6c427d0841..0000000000 --- a/arch/arm/include/asm/arch-tegra2/sdram_param.h +++ /dev/null @@ -1,148 +0,0 @@ -/* - * (C) Copyright 2010, 2011 - * NVIDIA Corporation <www.nvidia.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _SDRAM_PARAM_H_ -#define _SDRAM_PARAM_H_ - -/* - * Defines the number of 32-bit words provided in each set of SDRAM parameters - * for arbitration configuration data. - */ -#define BCT_SDRAM_ARB_CONFIG_WORDS 27 - -enum memory_type { - MEMORY_TYPE_NONE = 0, - MEMORY_TYPE_DDR, - MEMORY_TYPE_LPDDR, - MEMORY_TYPE_DDR2, - MEMORY_TYPE_LPDDR2, - MEMORY_TYPE_NUM, - MEMORY_TYPE_FORCE32 = 0x7FFFFFFF -}; - -/* Defines the SDRAM parameter structure */ -struct sdram_params { - enum memory_type memory_type; - u32 pllm_charge_pump_setup_control; - u32 pllm_loop_filter_setup_control; - u32 pllm_input_divider; - u32 pllm_feedback_divider; - u32 pllm_post_divider; - u32 pllm_stable_time; - u32 emc_clock_divider; - u32 emc_auto_cal_interval; - u32 emc_auto_cal_config; - u32 emc_auto_cal_wait; - u32 emc_pin_program_wait; - u32 emc_rc; - u32 emc_rfc; - u32 emc_ras; - u32 emc_rp; - u32 emc_r2w; - u32 emc_w2r; - u32 emc_r2p; - u32 emc_w2p; - u32 emc_rd_rcd; - u32 emc_wr_rcd; - u32 emc_rrd; - u32 emc_rext; - u32 emc_wdv; - u32 emc_quse; - u32 emc_qrst; - u32 emc_qsafe; - u32 emc_rdv; - u32 emc_refresh; - u32 emc_burst_refresh_num; - u32 emc_pdex2wr; - u32 emc_pdex2rd; - u32 emc_pchg2pden; - u32 emc_act2pden; - u32 emc_ar2pden; - u32 emc_rw2pden; - u32 emc_txsr; - u32 emc_tcke; - u32 emc_tfaw; - u32 emc_trpab; - u32 emc_tclkstable; - u32 emc_tclkstop; - u32 emc_trefbw; - u32 emc_quseextra; - u32 emc_fbioc_fg1; - u32 emc_fbio_dqsib_dly; - u32 emc_fbio_dqsib_dly_msb; - u32 emc_fbio_quse_dly; - u32 emc_fbio_quse_dly_msb; - u32 emc_fbio_cfg5; - u32 emc_fbio_cfg6; - u32 emc_fbio_spare; - u32 emc_mrs; - u32 emc_emrs; - u32 emc_mrw1; - u32 emc_mrw2; - u32 emc_mrw3; - u32 emc_mrw_reset_command; - u32 emc_mrw_reset_init_wait; - u32 emc_adr_cfg; - u32 emc_adr_cfg1; - u32 emc_emem_cfg; - u32 emc_low_latency_config; - u32 emc_cfg; - u32 emc_cfg2; - u32 emc_dbg; - u32 ahb_arbitration_xbar_ctrl; - u32 emc_cfg_dig_dll; - u32 emc_dll_xform_dqs; - u32 emc_dll_xform_quse; - u32 warm_boot_wait; - u32 emc_ctt_term_ctrl; - u32 emc_odt_write; - u32 emc_odt_read; - u32 emc_zcal_ref_cnt; - u32 emc_zcal_wait_cnt; - u32 emc_zcal_mrw_cmd; - u32 emc_mrs_reset_dll; - u32 emc_mrw_zq_init_dev0; - u32 emc_mrw_zq_init_dev1; - u32 emc_mrw_zq_init_wait; - u32 emc_mrs_reset_dll_wait; - u32 emc_emrs_emr2; - u32 emc_emrs_emr3; - u32 emc_emrs_ddr2_dll_enable; - u32 emc_mrs_ddr2_dll_reset; - u32 emc_emrs_ddr2_ocd_calib; - u32 emc_edr2_wait; - u32 emc_cfg_clktrim0; - u32 emc_cfg_clktrim1; - u32 emc_cfg_clktrim2; - u32 pmc_ddr_pwr; - u32 apb_misc_gp_xm2cfga_padctrl; - u32 apb_misc_gp_xm2cfgc_padctrl; - u32 apb_misc_gp_xm2cfgc_padctrl2; - u32 apb_misc_gp_xm2cfgd_padctrl; - u32 apb_misc_gp_xm2cfgd_padctrl2; - u32 apb_misc_gp_xm2clkcfg_padctrl; - u32 apb_misc_gp_xm2comp_padctrl; - u32 apb_misc_gp_xm2vttgen_padctrl; - u32 arbitration_config[BCT_SDRAM_ARB_CONFIG_WORDS]; -}; -#endif diff --git a/arch/arm/include/asm/arch-tegra2/sys_proto.h b/arch/arm/include/asm/arch-tegra2/sys_proto.h deleted file mode 100644 index c11534e585..0000000000 --- a/arch/arm/include/asm/arch-tegra2/sys_proto.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _SYS_PROTO_H_ -#define _SYS_PROTO_H_ - -struct tegra2_sysinfo { - char *board_string; -}; - -void invalidate_dcache(void); - -extern const struct tegra2_sysinfo sysinfo; - -#endif diff --git a/arch/arm/include/asm/arch-tegra2/tegra2.h b/arch/arm/include/asm/arch-tegra2/tegra2.h deleted file mode 100644 index 13d68c017c..0000000000 --- a/arch/arm/include/asm/arch-tegra2/tegra2.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _TEGRA2_H_ -#define _TEGRA2_H_ - -#define NV_PA_SDRAM_BASE 0x00000000 -#define NV_PA_ARM_PERIPHBASE 0x50040000 -#define NV_PA_PG_UP_BASE 0x60000000 -#define NV_PA_TMRUS_BASE 0x60005010 -#define NV_PA_CLK_RST_BASE 0x60006000 -#define NV_PA_FLOW_BASE 0x60007000 -#define NV_PA_GPIO_BASE 0x6000D000 -#define NV_PA_EVP_BASE 0x6000F000 -#define NV_PA_APB_MISC_BASE 0x70000000 -#define TEGRA2_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800) -#define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000) -#define NV_PA_APB_UARTB_BASE (NV_PA_APB_MISC_BASE + 0x6040) -#define NV_PA_APB_UARTC_BASE (NV_PA_APB_MISC_BASE + 0x6200) -#define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300) -#define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400) -#define TEGRA2_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380) -#define TEGRA2_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400) -#define TEGRA2_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800) -#define NV_PA_CSITE_BASE 0x70040000 -#define TEGRA_USB1_BASE 0xC5000000 -#define TEGRA_USB3_BASE 0xC5008000 -#define TEGRA_USB_ADDR_MASK 0xFFFFC000 - -#define TEGRA2_SDRC_CS0 NV_PA_SDRAM_BASE -#define LOW_LEVEL_SRAM_STACK 0x4000FFFC -#define EARLY_AVP_STACK (NV_PA_SDRAM_BASE + 0x20000) -#define EARLY_CPU_STACK (EARLY_AVP_STACK - 4096) -#define PG_UP_TAG_AVP 0xAAAAAAAA - -#ifndef __ASSEMBLY__ -struct timerus { - unsigned int cntr_1us; -}; - -/* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */ -#define AP20_WB_RUN_ADDRESS 0x40020000 - -#define NVBOOTINFOTABLE_BCTSIZE 0x38 /* BCT size in BIT in IRAM */ -#define NVBOOTINFOTABLE_BCTPTR 0x3C /* BCT pointer in BIT in IRAM */ -#define BCT_ODMDATA_OFFSET 4068 /* 12 bytes from end of BCT */ - -/* These are the available SKUs (product types) for Tegra */ -enum { - SKU_ID_T20 = 0x8, - SKU_ID_T25SE = 0x14, - SKU_ID_AP25 = 0x17, - SKU_ID_T25 = 0x18, - SKU_ID_AP25E = 0x1b, - SKU_ID_T25E = 0x1c, -}; - -/* These are the SOC categories that affect clocking */ -enum { - TEGRA_SOC_T20, - TEGRA_SOC_T25, - - TEGRA_SOC_COUNT, - TEGRA_SOC_UNKNOWN = -1, -}; - -#else /* __ASSEMBLY__ */ -#define PRM_RSTCTRL TEGRA2_PMC_BASE -#endif - -#endif /* TEGRA2_H */ diff --git a/arch/arm/include/asm/arch-tegra2/tegra_i2c.h b/arch/arm/include/asm/arch-tegra2/tegra_i2c.h deleted file mode 100644 index cfb136c466..0000000000 --- a/arch/arm/include/asm/arch-tegra2/tegra_i2c.h +++ /dev/null @@ -1,164 +0,0 @@ -/* - * NVIDIA Tegra2 I2C controller - * - * Copyright 2010-2011 NVIDIA Corporation - * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _TEGRA_I2C_H_ -#define _TEGRA_I2C_H_ - -#include <asm/types.h> - -enum { - I2C_TIMEOUT_USEC = 10000, /* Wait time for completion */ - I2C_FIFO_DEPTH = 8, /* I2C fifo depth */ -}; - -enum i2c_transaction_flags { - I2C_IS_WRITE = 0x1, /* for I2C write operation */ - I2C_IS_10_BIT_ADDRESS = 0x2, /* for 10-bit I2C slave address */ - I2C_USE_REPEATED_START = 0x4, /* for repeat start */ - I2C_NO_ACK = 0x8, /* for slave that won't generate ACK */ - I2C_SOFTWARE_CONTROLLER = 0x10, /* for I2C transfer using GPIO */ - I2C_NO_STOP = 0x20, -}; - -/* Contians the I2C transaction details */ -struct i2c_trans_info { - /* flags to indicate the transaction details */ - enum i2c_transaction_flags flags; - u32 address; /* I2C slave device address */ - u32 num_bytes; /* number of bytes to be transferred */ - /* - * Send/receive buffer. For the I2C send operation this buffer should - * be filled with the data to be sent to the slave device. For the I2C - * receive operation this buffer is filled with the data received from - * the slave device. - */ - u8 *buf; - int is_10bit_address; -}; - -struct i2c_control { - u32 tx_fifo; - u32 rx_fifo; - u32 packet_status; - u32 fifo_control; - u32 fifo_status; - u32 int_mask; - u32 int_status; -}; - -struct dvc_ctlr { - u32 ctrl1; /* 00: DVC_CTRL_REG1 */ - u32 ctrl2; /* 04: DVC_CTRL_REG2 */ - u32 ctrl3; /* 08: DVC_CTRL_REG3 */ - u32 status; /* 0C: DVC_STATUS_REG */ - u32 ctrl; /* 10: DVC_I2C_CTRL_REG */ - u32 addr_data; /* 14: DVC_I2C_ADDR_DATA_REG */ - u32 reserved_0[2]; /* 18: */ - u32 req; /* 20: DVC_REQ_REGISTER */ - u32 addr_data3; /* 24: DVC_I2C_ADDR_DATA_REG_3 */ - u32 reserved_1[6]; /* 28: */ - u32 cnfg; /* 40: DVC_I2C_CNFG */ - u32 cmd_addr0; /* 44: DVC_I2C_CMD_ADDR0 */ - u32 cmd_addr1; /* 48: DVC_I2C_CMD_ADDR1 */ - u32 cmd_data1; /* 4C: DVC_I2C_CMD_DATA1 */ - u32 cmd_data2; /* 50: DVC_I2C_CMD_DATA2 */ - u32 reserved_2[2]; /* 54: */ - u32 i2c_status; /* 5C: DVC_I2C_STATUS */ - struct i2c_control control; /* 60 ~ 78 */ -}; - -struct i2c_ctlr { - u32 cnfg; /* 00: I2C_I2C_CNFG */ - u32 cmd_addr0; /* 04: I2C_I2C_CMD_ADDR0 */ - u32 cmd_addr1; /* 08: I2C_I2C_CMD_DATA1 */ - u32 cmd_data1; /* 0C: I2C_I2C_CMD_DATA2 */ - u32 cmd_data2; /* 10: DVC_I2C_CMD_DATA2 */ - u32 reserved_0[2]; /* 14: */ - u32 status; /* 1C: I2C_I2C_STATUS */ - u32 sl_cnfg; /* 20: I2C_I2C_SL_CNFG */ - u32 sl_rcvd; /* 24: I2C_I2C_SL_RCVD */ - u32 sl_status; /* 28: I2C_I2C_SL_STATUS */ - u32 sl_addr1; /* 2C: I2C_I2C_SL_ADDR1 */ - u32 sl_addr2; /* 30: I2C_I2C_SL_ADDR2 */ - u32 reserved_1[2]; /* 34: */ - u32 sl_delay_count; /* 3C: I2C_I2C_SL_DELAY_COUNT */ - u32 reserved_2[4]; /* 40: */ - struct i2c_control control; /* 50 ~ 68 */ -}; - -/* bit fields definitions for IO Packet Header 1 format */ -#define PKT_HDR1_PROTOCOL_SHIFT 4 -#define PKT_HDR1_PROTOCOL_MASK (0xf << PKT_HDR1_PROTOCOL_SHIFT) -#define PKT_HDR1_CTLR_ID_SHIFT 12 -#define PKT_HDR1_CTLR_ID_MASK (0xf << PKT_HDR1_CTLR_ID_SHIFT) -#define PKT_HDR1_PKT_ID_SHIFT 16 -#define PKT_HDR1_PKT_ID_MASK (0xff << PKT_HDR1_PKT_ID_SHIFT) -#define PROTOCOL_TYPE_I2C 1 - -/* bit fields definitions for IO Packet Header 2 format */ -#define PKT_HDR2_PAYLOAD_SIZE_SHIFT 0 -#define PKT_HDR2_PAYLOAD_SIZE_MASK (0xfff << PKT_HDR2_PAYLOAD_SIZE_SHIFT) - -/* bit fields definitions for IO Packet Header 3 format */ -#define PKT_HDR3_READ_MODE_SHIFT 19 -#define PKT_HDR3_READ_MODE_MASK (1 << PKT_HDR3_READ_MODE_SHIFT) -#define PKT_HDR3_SLAVE_ADDR_SHIFT 0 -#define PKT_HDR3_SLAVE_ADDR_MASK (0x3ff << PKT_HDR3_SLAVE_ADDR_SHIFT) - -#define DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT 26 -#define DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK \ - (1 << DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT) - -/* I2C_CNFG */ -#define I2C_CNFG_NEW_MASTER_FSM_SHIFT 11 -#define I2C_CNFG_NEW_MASTER_FSM_MASK (1 << I2C_CNFG_NEW_MASTER_FSM_SHIFT) -#define I2C_CNFG_PACKET_MODE_SHIFT 10 -#define I2C_CNFG_PACKET_MODE_MASK (1 << I2C_CNFG_PACKET_MODE_SHIFT) - -/* I2C_SL_CNFG */ -#define I2C_SL_CNFG_NEWSL_SHIFT 2 -#define I2C_SL_CNFG_NEWSL_MASK (1 << I2C_SL_CNFG_NEWSL_SHIFT) - -/* I2C_FIFO_STATUS */ -#define TX_FIFO_FULL_CNT_SHIFT 0 -#define TX_FIFO_FULL_CNT_MASK (0xf << TX_FIFO_FULL_CNT_SHIFT) -#define TX_FIFO_EMPTY_CNT_SHIFT 4 -#define TX_FIFO_EMPTY_CNT_MASK (0xf << TX_FIFO_EMPTY_CNT_SHIFT) - -/* I2C_INTERRUPT_STATUS */ -#define I2C_INT_XFER_COMPLETE_SHIFT 7 -#define I2C_INT_XFER_COMPLETE_MASK (1 << I2C_INT_XFER_COMPLETE_SHIFT) -#define I2C_INT_NO_ACK_SHIFT 3 -#define I2C_INT_NO_ACK_MASK (1 << I2C_INT_NO_ACK_SHIFT) -#define I2C_INT_ARBITRATION_LOST_SHIFT 2 -#define I2C_INT_ARBITRATION_LOST_MASK (1 << I2C_INT_ARBITRATION_LOST_SHIFT) - -/** - * Returns the bus number of the DVC controller - * - * @return number of bus, or -1 if there is no DVC active - */ -int tegra_i2c_get_dvc_bus_num(void); - -#endif diff --git a/arch/arm/include/asm/arch-tegra2/tegra_spi.h b/arch/arm/include/asm/arch-tegra2/tegra_spi.h deleted file mode 100644 index 892d90c00b..0000000000 --- a/arch/arm/include/asm/arch-tegra2/tegra_spi.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * NVIDIA Tegra2 SPI-FLASH controller - * - * Copyright 2010-2012 NVIDIA Corporation - * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _TEGRA_SPI_H_ -#define _TEGRA_SPI_H_ - -#include <asm/types.h> - -struct spi_tegra { - u32 command; /* SPI_COMMAND_0 register */ - u32 status; /* SPI_STATUS_0 register */ - u32 rx_cmp; /* SPI_RX_CMP_0 register */ - u32 dma_ctl; /* SPI_DMA_CTL_0 register */ - u32 tx_fifo; /* SPI_TX_FIFO_0 register */ - u32 rsvd[3]; /* offsets 0x14 to 0x1F reserved */ - u32 rx_fifo; /* SPI_RX_FIFO_0 register */ -}; - -#define SPI_CMD_GO (1 << 30) -#define SPI_CMD_ACTIVE_SCLK_SHIFT 26 -#define SPI_CMD_ACTIVE_SCLK_MASK (3 << SPI_CMD_ACTIVE_SCLK_SHIFT) -#define SPI_CMD_CK_SDA (1 << 21) -#define SPI_CMD_ACTIVE_SDA_SHIFT 18 -#define SPI_CMD_ACTIVE_SDA_MASK (3 << SPI_CMD_ACTIVE_SDA_SHIFT) -#define SPI_CMD_CS_POL (1 << 16) -#define SPI_CMD_TXEN (1 << 15) -#define SPI_CMD_RXEN (1 << 14) -#define SPI_CMD_CS_VAL (1 << 13) -#define SPI_CMD_CS_SOFT (1 << 12) -#define SPI_CMD_CS_DELAY (1 << 9) -#define SPI_CMD_CS3_EN (1 << 8) -#define SPI_CMD_CS2_EN (1 << 7) -#define SPI_CMD_CS1_EN (1 << 6) -#define SPI_CMD_CS0_EN (1 << 5) -#define SPI_CMD_BIT_LENGTH (1 << 4) -#define SPI_CMD_BIT_LENGTH_MASK 0x0000001F - -#define SPI_STAT_BSY (1 << 31) -#define SPI_STAT_RDY (1 << 30) -#define SPI_STAT_RXF_FLUSH (1 << 29) -#define SPI_STAT_TXF_FLUSH (1 << 28) -#define SPI_STAT_RXF_UNR (1 << 27) -#define SPI_STAT_TXF_OVF (1 << 26) -#define SPI_STAT_RXF_EMPTY (1 << 25) -#define SPI_STAT_RXF_FULL (1 << 24) -#define SPI_STAT_TXF_EMPTY (1 << 23) -#define SPI_STAT_TXF_FULL (1 << 22) -#define SPI_STAT_SEL_TXRX_N (1 << 16) -#define SPI_STAT_CUR_BLKCNT (1 << 15) - -#define SPI_TIMEOUT 1000 -#define TEGRA2_SPI_MAX_FREQ 52000000 - -#endif /* _TEGRA_SPI_H_ */ diff --git a/arch/arm/include/asm/arch-tegra2/timer.h b/arch/arm/include/asm/arch-tegra2/timer.h deleted file mode 100644 index adefa2c6c1..0000000000 --- a/arch/arm/include/asm/arch-tegra2/timer.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* Tegra2 timer functions */ - -#ifndef _TEGRA2_TIMER_H -#define _TEGRA2_TIMER_H - -/* returns the current monotonic timer value in microseconds */ -unsigned long timer_get_us(void); - -#endif diff --git a/arch/arm/include/asm/arch-tegra2/uart-spi-switch.h b/arch/arm/include/asm/arch-tegra2/uart-spi-switch.h deleted file mode 100644 index 82ac180acd..0000000000 --- a/arch/arm/include/asm/arch-tegra2/uart-spi-switch.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _UART_SPI_SWITCH_H -#define _UART_SPI_SWITCH_H - -#if defined(CONFIG_SPI_UART_SWITCH) -/* - * Signal that we are about to use the UART. This unfortunate hack is - * required by Seaboard, which cannot use its console and SPI at the same - * time! If the board file provides this, the board config will declare it. - * Let this be a lesson for others. - */ -void pinmux_select_uart(void); - -/* - * Signal that we are about the use the SPI bus. - */ -void pinmux_select_spi(void); - -#else /* not CONFIG_SPI_UART_SWITCH */ - -static inline void pinmux_select_uart(void) {} -static inline void pinmux_select_spi(void) {} - -#endif - -#endif diff --git a/arch/arm/include/asm/arch-tegra2/uart.h b/arch/arm/include/asm/arch-tegra2/uart.h deleted file mode 100644 index aea29a7588..0000000000 --- a/arch/arm/include/asm/arch-tegra2/uart.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _UART_H_ -#define _UART_H_ - -/* UART registers */ -struct uart_ctlr { - uint uart_thr_dlab_0; /* UART_THR_DLAB_0_0, offset 00 */ - uint uart_ier_dlab_0; /* UART_IER_DLAB_0_0, offset 04 */ - uint uart_iir_fcr; /* UART_IIR_FCR_0, offset 08 */ - uint uart_lcr; /* UART_LCR_0, offset 0C */ - uint uart_mcr; /* UART_MCR_0, offset 10 */ - uint uart_lsr; /* UART_LSR_0, offset 14 */ - uint uart_msr; /* UART_MSR_0, offset 18 */ - uint uart_spr; /* UART_SPR_0, offset 1C */ - uint uart_irda_csr; /* UART_IRDA_CSR_0, offset 20 */ - uint uart_reserved[6]; /* Reserved, unused, offset 24-38*/ - uint uart_asr; /* UART_ASR_0, offset 3C */ -}; - -#define NVRM_PLLP_FIXED_FREQ_KHZ 216000 -#define NV_DEFAULT_DEBUG_BAUD 115200 - -#define UART_FCR_TRIGGER_3 0x30 /* Mask for trigger set at 3 */ - -#endif /* UART_H */ diff --git a/arch/arm/include/asm/arch-tegra2/usb.h b/arch/arm/include/asm/arch-tegra2/usb.h deleted file mode 100644 index 638033be50..0000000000 --- a/arch/arm/include/asm/arch-tegra2/usb.h +++ /dev/null @@ -1,252 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _TEGRA_USB_H_ -#define _TEGRA_USB_H_ - - -/* USB Controller (USBx_CONTROLLER_) regs */ -struct usb_ctlr { - /* 0x000 */ - uint id; - uint reserved0; - uint host; - uint device; - - /* 0x010 */ - uint txbuf; - uint rxbuf; - uint reserved1[2]; - - /* 0x020 */ - uint reserved2[56]; - - /* 0x100 */ - u16 cap_length; - u16 hci_version; - uint hcs_params; - uint hcc_params; - uint reserved3[5]; - - /* 0x120 */ - uint dci_version; - uint dcc_params; - uint reserved4[6]; - - /* 0x140 */ - uint usb_cmd; - uint usb_sts; - uint usb_intr; - uint frindex; - - /* 0x150 */ - uint reserved5; - uint periodic_list_base; - uint async_list_addr; - uint async_tt_sts; - - /* 0x160 */ - uint burst_size; - uint tx_fill_tuning; - uint reserved6; /* is this port_sc1 on some controllers? */ - uint icusb_ctrl; - - /* 0x170 */ - uint ulpi_viewport; - uint reserved7; - uint endpt_nak; - uint endpt_nak_enable; - - /* 0x180 */ - uint reserved; - uint port_sc1; - uint reserved8[6]; - - /* 0x1a0 */ - uint reserved9; - uint otgsc; - uint usb_mode; - uint endpt_setup_stat; - - /* 0x1b0 */ - uint reserved10[20]; - - /* 0x200 */ - uint reserved11[0x80]; - - /* 0x400 */ - uint susp_ctrl; - uint phy_vbus_sensors; - uint phy_vbus_wakeup_id; - uint phy_alt_vbus_sys; - - /* 0x410 */ - uint usb1_legacy_ctrl; - uint reserved12[3]; - - /* 0x420 */ - uint reserved13[56]; - - /* 0x500 */ - uint reserved14[64 * 3]; - - /* 0x800 */ - uint utmip_pll_cfg0; - uint utmip_pll_cfg1; - uint utmip_xcvr_cfg0; - uint utmip_bias_cfg0; - - /* 0x810 */ - uint utmip_hsrx_cfg0; - uint utmip_hsrx_cfg1; - uint utmip_fslsrx_cfg0; - uint utmip_fslsrx_cfg1; - - /* 0x820 */ - uint utmip_tx_cfg0; - uint utmip_misc_cfg0; - uint utmip_misc_cfg1; - uint utmip_debounce_cfg0; - - /* 0x830 */ - uint utmip_bat_chrg_cfg0; - uint utmip_spare_cfg0; - uint utmip_xcvr_cfg1; - uint utmip_bias_cfg1; -}; - - -/* USB1_LEGACY_CTRL */ -#define USB1_NO_LEGACY_MODE 1 - -#define VBUS_SENSE_CTL_SHIFT 1 -#define VBUS_SENSE_CTL_MASK (3 << VBUS_SENSE_CTL_SHIFT) -#define VBUS_SENSE_CTL_VBUS_WAKEUP 0 -#define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP 1 -#define VBUS_SENSE_CTL_AB_SESS_VLD 2 -#define VBUS_SENSE_CTL_A_SESS_VLD 3 - -/* USBx_IF_USB_SUSP_CTRL_0 */ -#define UTMIP_PHY_ENB (1 << 12) -#define UTMIP_RESET (1 << 11) -#define USB_PHY_CLK_VALID (1 << 7) - -/* USBx_UTMIP_MISC_CFG1 */ -#define UTMIP_PLLU_STABLE_COUNT_SHIFT 6 -#define UTMIP_PLLU_STABLE_COUNT_MASK \ - (0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT) -#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT 18 -#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK \ - (0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT) -#define UTMIP_PHY_XTAL_CLOCKEN (1 << 30) - -/* USBx_UTMIP_PLL_CFG1_0 */ -#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27 -#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \ - (0xf << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT) -#define UTMIP_XTAL_FREQ_COUNT_SHIFT 0 -#define UTMIP_XTAL_FREQ_COUNT_MASK 0xfff - -/* USBx_UTMIP_BIAS_CFG1_0 */ -#define UTMIP_BIAS_PDTRK_COUNT_SHIFT 3 -#define UTMIP_BIAS_PDTRK_COUNT_MASK \ - (0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT) - -#define UTMIP_DEBOUNCE_CFG0_SHIFT 0 -#define UTMIP_DEBOUNCE_CFG0_MASK 0xffff - -/* USBx_UTMIP_TX_CFG0_0 */ -#define UTMIP_FS_PREAMBLE_J (1 << 19) - -/* USBx_UTMIP_BAT_CHRG_CFG0_0 */ -#define UTMIP_PD_CHRG 1 - -/* USBx_UTMIP_XCVR_CFG0_0 */ -#define UTMIP_XCVR_LSBIAS_SE (1 << 21) - -/* USBx_UTMIP_SPARE_CFG0_0 */ -#define FUSE_SETUP_SEL (1 << 3) - -/* USBx_UTMIP_HSRX_CFG0_0 */ -#define UTMIP_IDLE_WAIT_SHIFT 15 -#define UTMIP_IDLE_WAIT_MASK (0x1f << UTMIP_IDLE_WAIT_SHIFT) -#define UTMIP_ELASTIC_LIMIT_SHIFT 10 -#define UTMIP_ELASTIC_LIMIT_MASK \ - (0x1f << UTMIP_ELASTIC_LIMIT_SHIFT) - -/* USBx_UTMIP_HSRX_CFG0_1 */ -#define UTMIP_HS_SYNC_START_DLY_SHIFT 1 -#define UTMIP_HS_SYNC_START_DLY_MASK \ - (0xf << UTMIP_HS_SYNC_START_DLY_SHIFT) - -/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */ -#define IC_ENB1 (1 << 3) - -/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */ -#define PTS_SHIFT 30 -#define PTS_MASK (3U << PTS_SHIFT) -#define PTS_UTMI 0 -#define PTS_RESERVED 1 -#define PTS_ULP 2 -#define PTS_ICUSB_SER 3 - -#define STS (1 << 29) - -/* USBx_UTMIP_XCVR_CFG0_0 */ -#define UTMIP_FORCE_PD_POWERDOWN (1 << 14) -#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16) -#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18) - -/* USBx_UTMIP_XCVR_CFG1_0 */ -#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0) -#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2) -#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4) - -/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */ -#define VBUS_VLD_STS (1 << 26) - - -/* Change the USB host port into host mode */ -void usb_set_host_mode(void); - -/* Setup USB on the board */ -int board_usb_init(const void *blob); - -/** - * Start up the given port number (ports are numbered from 0 on each board). - * This returns values for the appropriate hccr and hcor addresses to use for - * USB EHCI operations. - * - * @param portnum port number to start - * @param hccr returns start address of EHCI HCCR registers - * @param hcor returns start address of EHCI HCOR registers - * @return 0 if ok, -1 on error (generally invalid port number) - */ -int tegrausb_start_port(unsigned portnum, u32 *hccr, u32 *hcor); - -/** - * Stop the current port - * - * @return 0 if ok, -1 if no port was active - */ -int tegrausb_stop_port(void); - -#endif /* _TEGRA_USB_H_ */ diff --git a/arch/arm/include/asm/arch-tegra2/warmboot.h b/arch/arm/include/asm/arch-tegra2/warmboot.h deleted file mode 100644 index 99ac2e7d23..0000000000 --- a/arch/arm/include/asm/arch-tegra2/warmboot.h +++ /dev/null @@ -1,150 +0,0 @@ -/* - * (C) Copyright 2010, 2011 - * NVIDIA Corporation <www.nvidia.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _WARM_BOOT_H_ -#define _WARM_BOOT_H_ - -#define STRAP_OPT_A_RAM_CODE_SHIFT 4 -#define STRAP_OPT_A_RAM_CODE_MASK (0xf << STRAP_OPT_A_RAM_CODE_SHIFT) - -/* Defines the supported operating modes */ -enum fuse_operating_mode { - MODE_PRODUCTION = 3, - MODE_UNDEFINED, -}; - -/* Defines the CMAC-AES-128 hash length in 32 bit words. (128 bits = 4 words) */ -enum { - HASH_LENGTH = 4 -}; - -/* Defines the storage for a hash value (128 bits) */ -struct hash { - u32 hash[HASH_LENGTH]; -}; - -/* - * Defines the code header information for the boot rom. - * - * The code immediately follows the code header. - * - * Note that the code header needs to be 16 bytes aligned to preserve - * the alignment of relevant data for hash and decryption computations without - * requiring extra copies to temporary memory areas. - */ -struct wb_header { - u32 length_insecure; /* length of the code header */ - u32 reserved[3]; - struct hash hash; /* hash of header+code, starts next field*/ - struct hash random_aes_block; /* a data block to aid security. */ - u32 length_secure; /* length of the code header */ - u32 destination; /* destination address to put the wb code */ - u32 entry_point; /* execution address of the wb code */ - u32 code_length; /* length of the code */ -}; - -/* - * The warm boot code needs direct access to these registers since it runs in - * SRAM and cannot call other U-Boot code. - */ -union osc_ctrl_reg { - struct { - u32 xoe:1; - u32 xobp:1; - u32 reserved0:2; - u32 xofs:6; - u32 reserved1:2; - u32 xods:5; - u32 reserved2:3; - u32 oscfi_spare:8; - u32 pll_ref_div:2; - u32 osc_freq:2; - }; - u32 word; -}; - -union pllx_base_reg { - struct { - u32 divm:5; - u32 reserved0:3; - u32 divn:10; - u32 reserved1:2; - u32 divp:3; - u32 reserved2:4; - u32 lock:1; - u32 reserved3:1; - u32 ref_dis:1; - u32 enable:1; - u32 bypass:1; - }; - u32 word; -}; - -union pllx_misc_reg { - struct { - u32 vcocon:4; - u32 lfcon:4; - u32 cpcon:4; - u32 lock_sel:6; - u32 reserved0:1; - u32 lock_enable:1; - u32 reserved1:1; - u32 dccon:1; - u32 pts:2; - u32 reserved2:6; - u32 out1_div_byp:1; - u32 out1_inv_clk:1; - }; - u32 word; -}; - -/* - * TODO: This register is not documented in the TRM yet. We could move this - * into the EMC and give it a proper interface, but not while it is - * undocumented. - */ -union scratch3_reg { - struct { - u32 pllx_base_divm:5; - u32 pllx_base_divn:10; - u32 pllx_base_divp:3; - u32 pllx_misc_lfcon:4; - u32 pllx_misc_cpcon:4; - }; - u32 word; -}; - - -/** - * Save warmboot memory settings for a later resume - * - * @return 0 if ok, -1 on error - */ -int warmboot_save_sdram_params(void); - -int warmboot_prepare_code(u32 seg_address, u32 seg_length); -int sign_data_block(u8 *source, u32 length, u8 *signature); -void wb_start(void); /* Start of WB assembly code */ -void wb_end(void); /* End of WB assembly code */ - -#endif |