diff options
| author | Tom Warren <twarren@nvidia.com> | 2015-06-25 09:50:44 -0700 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2015-08-05 15:22:51 -0700 |
| commit | 722e000ccd7226c5cd071590b5361620eb0b126c (patch) | |
| tree | 257ddcaf4039dd6722e743e8a1f4035c2f85387f /arch/arm/include/asm/arch-tegra/clk_rst.h | |
| parent | 3e8650c0f9cc7fb29bd75c11d0173768fcc80203 (diff) | |
Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.
Added PLL variables (dividers mask/shift, lock enable/detect, etc.)
to new pllinfo struct for each Soc/PLL. PLLA/C/D/E/M/P/U/X.
Used pllinfo struct in all clock functions, validated on T210.
Should be equivalent to prior code on T124/114/30/20. Thanks
to Marcel Ziswiler for corrections to the T20/T30 values.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/include/asm/arch-tegra/clk_rst.h')
| -rw-r--r-- | arch/arm/include/asm/arch-tegra/clk_rst.h | 32 |
1 files changed, 3 insertions, 29 deletions
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h index f69026002b4..ee9436e2e53 100644 --- a/arch/arm/include/asm/arch-tegra/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra/clk_rst.h @@ -249,17 +249,6 @@ struct clk_rst_ctlr { #define PLL_LOCK_SHIFT 27 #define PLL_LOCK_MASK (1U << PLL_LOCK_SHIFT) -#define PLL_DIVP_SHIFT 20 -#define PLL_DIVP_MASK (7U << PLL_DIVP_SHIFT) -/* Special case for T210 PLLU DIVP */ -#define PLLU_DIVP_SHIFT 16 - -#define PLL_DIVN_SHIFT 8 -#define PLL_DIVN_MASK (0x3ffU << PLL_DIVN_SHIFT) - -#define PLL_DIVM_SHIFT 0 -#define PLL_DIVM_MASK (0x1f << PLL_DIVM_SHIFT) - /* CLK_RST_CONTROLLER_PLLx_OUTx_0 */ #define PLL_OUT_RSTN (1 << 0) #define PLL_OUT_CLKEN (1 << 1) @@ -272,24 +261,6 @@ struct clk_rst_ctlr { #define PLL_DCCON_SHIFT 20 #define PLL_DCCON_MASK (1U << PLL_DCCON_SHIFT) -#define PLL_LOCK_ENABLE_SHIFT 18 -#define PLL_LOCK_ENABLE_MASK (1U << PLL_LOCK_ENABLE_SHIFT) - -#define PLL_CPCON_SHIFT 8 -#define PLL_CPCON_MASK (15U << PLL_CPCON_SHIFT) - -#define PLL_LFCON_SHIFT 4 -#define PLL_LFCON_MASK (15U << PLL_LFCON_SHIFT) - -/* CPCON/LFCON replaced by KCP/KVCO in T210 PLLU */ -#define PLLU_KVCO_SHIFT 24 -#define PLLU_KVCO_MASK (3U << PLLU_KVCO_SHIFT) -#define PLLU_KCP_SHIFT 25 -#define PLLU_KCP_MASK (1U << PLLU_KCP_SHIFT) - -#define PLLU_VCO_FREQ_SHIFT 20 -#define PLLU_VCO_FREQ_MASK (1U << PLLU_VCO_FREQ_SHIFT) - #define PLLP_OUT1_OVR (1 << 2) #define PLLP_OUT2_OVR (1 << 18) #define PLLP_OUT3_OVR (1 << 2) @@ -475,4 +446,7 @@ enum { #define PLLDP_SS_CFG_UNDOCUMENTED (1 << 24) #define PLLDP_SS_CFG_DITHER (1 << 28) +/* CLK_RST_PLLD_MISC */ +#define PLLD_CLKENABLE 30 + #endif /* _TEGRA_CLK_RST_H_ */ |