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authorPatrice Chotard <patrice.chotard@st.com>2017-11-15 13:14:52 +0100
committerTom Rini <trini@konsulko.com>2017-11-29 22:30:50 -0500
commit4e97e25723530cc8bf57ca1d0ae17d86895e04c5 (patch)
tree776fe7bae3a58cde68b6b024427436d41c22dfa1 /arch/arm/include/asm/arch-stm32f7
parent928954fe58e69767b138816ab58e1a7e48f2c685 (diff)
clk: clk_stm32fx: add clock configuration for mmc usage
MMC block needs 48Mhz source clock, for that we choose to select the SAI PLL. Update also stm32_clock_get_rate() to retrieve the MMC clock source needed in MMC driver. STM32F4 uses a different RCC variant than STM32F7. For STM32F4 sdmmc clocks bit are located into dckcfgr register whereas there are located into dckcfgr2 registers on STM32F7. In both registers, bits CK48MSEL and SDMMC1SEL are located at the same position. Signed-off-by: Christophe Priouzeau <christophe.priouzeau@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
Diffstat (limited to 'arch/arm/include/asm/arch-stm32f7')
-rw-r--r--arch/arm/include/asm/arch-stm32f7/stm32.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h b/arch/arm/include/asm/arch-stm32f7/stm32.h
index 0117039cf2..f5e08ef8f5 100644
--- a/arch/arm/include/asm/arch-stm32f7/stm32.h
+++ b/arch/arm/include/asm/arch-stm32f7/stm32.h
@@ -92,6 +92,7 @@ struct stm32_rcc_regs {
u32 plli2scfgr; /* RCC PLLI2S configuration */
u32 pllsaicfgr; /* PLLSAI configuration */
u32 dckcfgr; /* dedicated clocks configuration register */
+ u32 dckcfgr2; /* dedicated clocks configuration register */
};
#define STM32_RCC ((struct stm32_rcc_regs *)RCC_BASE)