MLK-18146-2 mx6: Update registers mapping file

Update the CCM and AIPS registers mapping files to align with v2017.03

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 4479d29d344c89fe3f0ba73934e72bc6099b6eaf)
(cherry picked from commit 079cfb35c0a898d0cb3f6441c5dc41e06edb6525)
(cherry picked from commit 170a48574588ddcf475811182dc697938da63454)
(cherry picked from commit 9b25d90c6d7035842c1df10e3a24315eeb205946)
(cherry picked from commit cab5e2c3650d202dc4e7fdf01b35af302693ac9a)

2 files changed, 158 insertions, 27 deletions

diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index 2a2b8dd806..5ef17f0cc9 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -264,11 +264,20 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET		29
 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK		(0x7 << 26)
 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET		26
-/* LCDIF on i.MX6SX/UL */
+/* LCDIF on i.MX6SX/UL/SLL */
 #define MXC_CCM_CBCMR_LCDIF1_PODF_MASK                  (0x7 << 23)
 #define MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET                23
-#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK		(0x7 << 23)
-#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET		23
+#define MXC_CCM_CBCMR_GPU2D_CORE_CLK_PODF_MASK		(0x7 << 23)
+#define MXC_CCM_CBCMR_GPU2D_CORE_CLK_PODF_OFFSET		23
+
+/* For i.MX6SL */
+#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK		(0x7 << 29)
+#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET		29
+#define MXC_CCM_CBCMR_GPU2D_OVG_CORE_PODF_MASK		(0x7 << 26)
+#define MXC_CCM_CBCMR_GPU2D_OVG_CORE_PODF_OFFSET		26
+#define MXC_CCM_CBCMR_EPDC_PIX_PODF_MASK		(0x7 << 23)
+#define MXC_CCM_CBCMR_EPDC_PIX_PODF_OFFSET		23
+
 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK		(0x3 << 21)
 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET	21
 #define MXC_CCM_CBCMR_PERIPH2_CLK2_SEL			(1 << 20)
@@ -290,6 +299,14 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET	8
 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK		(0x3 << 4)
 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET		4
+
+/* For i.MX6SL */
+#define MXC_CCM_CBCMR_GPU2D_CORE_CLK_SEL_MASK		(0x3 << 8)
+#define MXC_CCM_CBCMR_GPU2D_CORE_CLK_SEL_OFFSET	8
+#define MXC_CCM_CBCMR_GPU2D_OVG_CORE_CLK_SEL_MASK		(0x3 << 4)
+#define MXC_CCM_CBCMR_GPU2D_OVG_CORE_CLK_SEL_OFFSET		4
+
+
 /* Exists on i.MX6QP */
 #define MXC_CCM_CBCMR_PRE_CLK_SEL			(1 << 1)
 
@@ -431,15 +448,15 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v)		(((v) & 0x3) << 16)
 
 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK		\
-	((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ?	\
+	((is_mx6dqp() || is_mx6ul() || is_mx6ull()) ? \
 	 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP :		\
 	 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ)
 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET		\
-	((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ?	\
+	((is_mx6dqp() || is_mx6ul() || is_mx6ull()) ? \
 	 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP :	\
 	 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ)
 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v)			\
-	((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ?	\
+	((is_mx6dqp() || is_mx6ul() || is_mx6ull()) ? \
 	 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) :		\
 	 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v))
 
@@ -499,7 +516,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK		(0x7)
 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET		0
 
-/* i.MX6ULL */
+/* i.MX6ULL/SLL */
 #define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_MASK		(0x7 << 15)
 #define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_OFFSET		15
 #define MXC_CCM_CHSCCDR_EPDC_PODF_MASK			(0x7 << 12)
@@ -516,13 +533,20 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET		19
 /* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */
 #define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK		(0x1 << 18)
-/* LCDIF1 on i.MX6SX/UL */
+/* LCDIF1 on i.MX6SX/UL/SLL */
 #define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK             (0x7 << 15)
 #define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET           15
 #define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK              (0x7 << 12)
 #define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET            12
 #define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK              (0x7 << 9)
 #define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_OFFSET            9
+
+/* EPDC on i.MX6SL */
+#define MXC_CCM_CSCDR2_EPDC_PIX_CLK_SEL_MASK             (0x7 << 15)
+#define MXC_CCM_CSCDR2_EPDC_PIX_CLK_SEL_OFFSET           15
+#define MXC_CCM_CSCDR2_EPDC_PIX_PRE_DIV_MASK              (0x7 << 12)
+#define MXC_CCM_CSCDR2_EPDC_PIX_PRE_DIV_OFFSET            12
+
 /* LCDIF2 on i.MX6SX */
 #define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK             (0x7 << 6)
 #define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET           6
@@ -567,6 +591,16 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCDR3_LCDIF_AXI_PODF_OFFSET		16
 #define MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK		(0x3 << 14)
 #define MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET		14
+#define MXC_CCM_CSCDR3_CSI_CORE_PODF_MASK		(0x7 << 11)
+#define MXC_CCM_CSCDR3_CSI_CORE_PODF_OFFSET		11
+#define MXC_CCM_CSCDR3_CSI_CORE_CLK_SEL_MASK		(0x3 << 9)
+#define MXC_CCM_CSCDR3_CSI_CORE_CLK_SEL_OFFSET		9
+
+/* For i.MX6SLL */
+#define MXC_CCM_CSCDR3_PXP_PODF_MASK		(0x7 << 16)
+#define MXC_CCM_CSCDR3_PXP_PODF_OFFSET		16
+#define MXC_CCM_CSCDR3_PXP_CLK_SEL_MASK		(0x3 << 14)
+#define MXC_CCM_CSCDR3_PXP_CLK_SEL_OFFSET		14
 
 /* Define the bits in register CDHIPR */
 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY			(1 << 16)
@@ -769,7 +803,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR2_IPMUX3_MASK			(3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET	22
 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK	(3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
-/* i.MX6SX/UL LCD and PXP */
+/* i.MX6SX/UL/SLL LCD and PXP */
 #define MXC_CCM_CCGR2_LCD_OFFSET			28
 #define MXC_CCM_CCGR2_LCD_MASK				(3 << MXC_CCM_CCGR2_LCD_OFFSET)
 #define MXC_CCM_CCGR2_PXP_OFFSET			30
@@ -798,10 +832,18 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR3_QSPI_MASK					(3 << MXC_CCM_CCGR3_QSPI_OFFSET)
 
 /* i.MX6SL */
-#define MXC_CCM_CCGR3_LCDIF_AXI_OFFSET				6
-#define MXC_CCM_CCGR3_LCDIF_AXI_MASK				(3 << MXC_CCM_CCGR3_LCDIF_AXI_OFFSET)
-#define MXC_CCM_CCGR3_LCDIF_PIX_OFFSET				8
-#define MXC_CCM_CCGR3_LCDIF_PIX_MASK				(3 << MXC_CCM_CCGR3_LCDIF_PIX_OFFSET)
+#define MXC_CCM_CCGR3_CSI_CORE_OFFSET			0
+#define MXC_CCM_CCGR3_CSI_CORE_MASK				(3 << MXC_CCM_CCGR3_CSI_CORE_OFFSET)
+#define MXC_CCM_CCGR3_PXP_AXI_OFFSET			2
+#define MXC_CCM_CCGR3_PXP_AXI_MASK				(3 << MXC_CCM_CCGR3_PXP_AXI_OFFSET)
+#define MXC_CCM_CCGR3_EPDC_AXI_OFFSET			4
+#define MXC_CCM_CCGR3_EPDC_AXI_MASK				(3 << MXC_CCM_CCGR3_EPDC_AXI_OFFSET)
+#define MXC_CCM_CCGR3_LCDIF_AXI_OFFSET			6
+#define MXC_CCM_CCGR3_LCDIF_AXI_MASK			(3 << MXC_CCM_CCGR3_LCDIF_AXI_OFFSET)
+#define MXC_CCM_CCGR3_LCDIF_PIX_OFFSET			8
+#define MXC_CCM_CCGR3_LCDIF_PIX_MASK			(3 << MXC_CCM_CCGR3_LCDIF_PIX_OFFSET)
+#define MXC_CCM_CCGR3_EPDC_PIX_OFFSET			10
+#define MXC_CCM_CCGR3_EPDC_PIX_MASK				(3 << MXC_CCM_CCGR3_EPDC_PIX_OFFSET)
 
 #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET				0
 #define MXC_CCM_CCGR3_IPU1_IPU_MASK				(3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 6f10c879b8..28063388b2 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -122,7 +122,7 @@
 #define MMDC1_ARB_END_ADDR              0xFFFFFFFF
 #endif
 
-#ifndef CONFIG_MX6SX
+#if (!(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL)))
 #define IPU_SOC_BASE_ADDR		IPU1_ARB_BASE_ADDR
 #define IPU_SOC_OFFSET			0x00200000
 #endif
@@ -158,12 +158,21 @@
 #define UART1_BASE                  (ATZ1_BASE_ADDR + 0x20000)
 #define ESAI1_BASE_ADDR             (ATZ1_BASE_ADDR + 0x24000)
 #define UART8_BASE                  (ATZ1_BASE_ADDR + 0x24000)
+#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#define SAI1_BASE_ADDR              (ATZ1_BASE_ADDR + 0x28000)
+#define SAI2_BASE_ADDR              (ATZ1_BASE_ADDR + 0x2C000)
+#define SAI3_BASE_ADDR              (ATZ1_BASE_ADDR + 0x30000)
+#else
 #define SSI1_BASE_ADDR              (ATZ1_BASE_ADDR + 0x28000)
 #define SSI2_BASE_ADDR              (ATZ1_BASE_ADDR + 0x2C000)
 #define SSI3_BASE_ADDR              (ATZ1_BASE_ADDR + 0x30000)
+#endif
 #define ASRC_BASE_ADDR              (ATZ1_BASE_ADDR + 0x34000)
 
-#ifndef CONFIG_MX6SX
+#if defined(CONFIG_MX6UL)
+#define TOUCH_CTRL_BASE_ADDR        (ATZ1_BASE_ADDR + 0x40000)
+#define BEE_BASE_ADDR               (ATZ1_BASE_ADDR + 0x44000)
+#elif !defined(CONFIG_MX6SX)
 #define SPBA_BASE_ADDR              (ATZ1_BASE_ADDR + 0x3C000)
 #define VPU_BASE_ADDR               (ATZ1_BASE_ADDR + 0x40000)
 #endif
@@ -185,8 +194,13 @@
 #define GPIO4_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x28000)
 #define GPIO5_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x2C000)
 #define MX6UL_SNVS_LP_BASE_ADDR     (AIPS1_OFF_BASE_ADDR + 0x30000)
+#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#define SNVS_LP_BASE_ADDR           (AIPS1_OFF_BASE_ADDR + 0x30000)
+#define ENET2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x34000)
+#else
 #define GPIO6_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x30000)
 #define GPIO7_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x34000)
+#endif
 #define KPP_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x38000)
 #define WDOG1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x3C000)
 #define WDOG2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x40000)
@@ -211,6 +225,7 @@
 #define CSI_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x64000)
 #define SIPIX_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x68000)
 #define SDMA_PORT_HOST_BASE_ADDR    (AIPS1_OFF_BASE_ADDR + 0x6C000)
+#define EPDC_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x74000)
 #elif defined(CONFIG_MX6SX)
 #define CANFD1_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x68000)
 #define SDMA_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x6C000)
@@ -218,10 +233,19 @@
 #define SEMAPHORE1_BASE_ADDR        (AIPS1_OFF_BASE_ADDR + 0x74000)
 #define SEMAPHORE2_BASE_ADDR        (AIPS1_OFF_BASE_ADDR + 0x78000)
 #define RDC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x7C000)
+
+#elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#define GPT2_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x68000)
+#define SDMA_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x6C000)
+#define PWM5_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x70000)
+#define PWM6_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x74000)
+#define PWM7_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x78000)
+#define PWM8_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x7C000)
 #else
 #define DCIC1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x64000)
 #define DCIC2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x68000)
 #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
+#define EPDC_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x74000)
 #endif
 
 #define MX6SL_LCDIF_BASE_ADDR      (AIPS1_OFF_BASE_ADDR + 0x78000)
@@ -231,12 +255,14 @@
 #define AIPS2_OFF_BASE_ADDR         (ATZ2_BASE_ADDR + 0x80000)
 #define AIPS3_ON_BASE_ADDR          (ATZ3_BASE_ADDR + 0x7C000)
 #define AIPS3_OFF_BASE_ADDR         (ATZ3_BASE_ADDR + 0x80000)
+
 #if defined(CONFIG_MX6UL)
 #define CAAM_BASE_ADDR              (ATZ2_BASE_ADDR + 0x40000)
+#define ARM_BASE_ADDR               (ATZ2_BASE_ADDR)
 #else
 #define CAAM_BASE_ADDR              (ATZ2_BASE_ADDR)
+#define ARM_BASE_ADDR		    	(ATZ2_BASE_ADDR + 0x40000)
 #endif
-#define ARM_BASE_ADDR		    (ATZ2_BASE_ADDR + 0x40000)
 
 #define CONFIG_SYS_FSL_SEC_OFFSET   0
 #define CONFIG_SYS_FSL_SEC_ADDR     (CAAM_BASE_ADDR + \
@@ -252,6 +278,8 @@
 #define ENET_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x8000)
 #ifdef CONFIG_MX6SL
 #define MSHC_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0xC000)
+#elif defined(CONFIG_MX6UL)
+#define SIM1_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0xC000)
 #else
 #define MLB_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0xC000)
 #endif
@@ -260,6 +288,9 @@
 #define USDHC2_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x14000)
 #define USDHC3_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x18000)
 #define USDHC4_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x1C000)
+
+#define MX6UL_ADC1_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x18000)
+#define MX6UL_ADC2_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x1C000)
 #define I2C1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x20000)
 #define I2C2_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x24000)
 #define I2C3_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x28000)
@@ -279,12 +310,16 @@
 #define WEIM_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x38000)
 #define OCOTP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x3C000)
 #define CSU_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x40000)
-#ifdef CONFIG_MX6SLL
+#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#define CSI_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x44000)
+#define PXP_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x4C000)
+#elif defined(CONFIG_MX6SLL)
 #define IOMUXC_GPR_SNVS_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x44000)
 #define IOMUXC_SNVS_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x48000)
-#endif
+#else
 #define IP2APB_PERFMON1_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x44000)
 #define IP2APB_PERFMON2_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x48000)
+#endif
 #define MX6UL_LCDIF1_BASE_ADDR      (AIPS2_OFF_BASE_ADDR + 0x48000)
 #define MX6ULL_LCDIF1_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x48000)
 #ifdef CONFIG_MX6SX
@@ -294,9 +329,10 @@
 #endif
 #define IP2APB_TZASC1_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x50000)
 #if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
-#define SCTR_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x5C000)
+#define SYSCNT_RD_IPS_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x54000)
+#define SYSCNT_CMP_IPS_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x58000)
+#define SYSCNT_CTRL_IPS_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x5C000)
 #define QSPI0_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
-#define UART6_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x7C000)
 #elif defined(CONFIG_MX6SX)
 #define SAI1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x54000)
 #define AUDMUX_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x58000)
@@ -314,9 +350,20 @@
 #define UART3_BASE                  (AIPS2_OFF_BASE_ADDR + 0x6C000)
 #define UART4_BASE                  (AIPS2_OFF_BASE_ADDR + 0x70000)
 #define UART5_BASE                  (AIPS2_OFF_BASE_ADDR + 0x74000)
+/* i.MX6SLL */
+#define MTR_MASTER_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x7C000)
+/* i.MX6SX/UL */
 #define I2C4_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x78000)
+/* i.MX6UL */
+#define MX6UL_UART6_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x7C000)
 #define IP2APB_USBPHY1_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x78000)
 #define IP2APB_USBPHY2_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x7C000)
+
+#define OTG_BASE_ADDR               USB_BASE_ADDR
+
+#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#define SCTR_BASE_ADDR              SYSCNT_CTRL_IPS_BASE_ADDR
+#endif
 /* i.MX6SLL */
 #define MTR_MASTER_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x7C000)
 
@@ -331,19 +378,18 @@
 #define VDEC_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x2C000)
 #define SPBA_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x3C000)
 #define AIPS3_CONFIG_BASE_ADDR      (AIPS3_ARB_BASE_ADDR + 0x7C000)
-#define ADC1_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x80000)
-#define ADC2_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x84000)
+#define MX6SX_ADC1_BASE_ADDR        (AIPS3_ARB_BASE_ADDR + 0x80000)
+#define MX6SX_ADC2_BASE_ADDR        (AIPS3_ARB_BASE_ADDR + 0x84000)
 #define ECSPI5_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x8C000)
 #define HS_BASE_ADDR                (AIPS3_ARB_BASE_ADDR + 0x90000)
 #define MU_MCU_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x94000)
 #define CANFD_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x98000)
 #define MU_DSP_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x9C000)
-#define UART6_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0xA0000)
 #define PWM5_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xA4000)
 #define PWM6_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xA8000)
 #define PWM7_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xAC000)
 #define PWM8_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xB0000)
-#elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#elif defined(CONFIG_MX6ULL)
 #define AIPS3_CONFIG_BASE_ADDR      (AIPS3_ARB_BASE_ADDR + 0x7C000)
 #define DCP_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x80000)
 #define RNGB_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x84000)
@@ -359,6 +405,7 @@
 #define LCDIF2_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x24000)
 #define MX6SX_LCDIF1_BASE_ADDR      (AIPS3_ARB_BASE_ADDR + 0x20000)
 #define MX6SX_WDOG3_BASE_ADDR       (AIPS3_ARB_BASE_ADDR + 0x88000)
+#define MX6SX_UART6_BASE_ADDR       (AIPS3_ARB_BASE_ADDR + 0xA0000)
 
 #if !(defined(CONFIG_MX6SX) || \
 	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
@@ -368,6 +415,7 @@
 #define IRAM_SIZE                    0x00020000
 #endif
 #define FEC_QUIRK_ENET_MAC
+#define SNVS_LPGPR                   0x68
 
 #include <asm/mach-imx/regs-lcdif.h>
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
@@ -385,6 +433,12 @@
 			  MX6UL_LCDIF1_BASE_ADDR :		\
 			  ((is_mx6ull()) ?	\
 			  MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR)))
+#define UART6_BASE_ADDR ((is_mx6ul() || is_mx6ull()) ? \
+			  MX6UL_UART6_BASE_ADDR : MX6SX_UART6_BASE_ADDR)
+
+#define MXS_LCDIF_BASE LCDIF1_BASE_ADDR
+
+#define MXS_LCDIF_BASE LCDIF1_BASE_ADDR
 
 
 extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
@@ -585,7 +639,12 @@ struct iomuxc {
 #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
 	u8 reserved[0x4000];
 #endif
+
+#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+	u32 gpr[15];
+#else
 	u32 gpr[14];
+#endif
 };
 
 struct gpc {
@@ -668,10 +727,19 @@ struct gpc {
 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0		(IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1		(IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
 
-/*
- * CSPI register definitions
- */
+#define IMX6SX_GPR5_CSI1_MUX_CTRL_MASK			(0x3 << 4)
+#define IMX6SX_GPR5_CSI1_MUX_CTRL_EXT_PIN		(0x0 << 4)
+#define IMX6SX_GPR5_CSI1_MUX_CTRL_CVD			(0x1 << 4)
+#define IMX6SX_GPR5_CSI1_MUX_CTRL_VDAC_TO_CSI	(0x2 << 4)
+#define IMX6SX_GPR5_CSI1_MUX_CTRL_GND			(0x3 << 4)
+
+#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) ||\
+	defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL)
+#define SPI_MAX_NUM	3
+#else
 #define SPI_MAX_NUM	4
+#endif
+
 #if defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
 	defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
 #define MXC_SPI_BASE_ADDRESSES \
@@ -688,6 +756,8 @@ struct gpc {
 	ECSPI5_BASE_ADDR
 #endif
 
+#define ANATOP_PLL_VIDEO        0xA0
+
 struct ocotp_regs {
 	u32	ctrl;
 	u32	ctrl_set;
@@ -937,6 +1007,25 @@ struct anatop_regs {
 #define ANATOP_PFD_CLKGATE_SHIFT(n)	(7+((n)*8))
 #define ANATOP_PFD_CLKGATE_MASK(n)	(1<<ANATOP_PFD_CLKGATE_SHIFT(n))
 
+struct iomuxc_gpr_base_regs {
+#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+	u32     gpr[15];        /* 0x000 */
+#else
+	u32     gpr[14];        /* 0x000 */
+#endif
+};
+
+struct iomuxc_base_regs {
+#if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+	u32     gpr[14];        /* 0x000 */
+#endif
+	u32     obsrv[5];       /* 0x038 */
+	u32     swmux_ctl[197]; /* 0x04c */
+	u32     swpad_ctl[250]; /* 0x360 */
+	u32     swgrp[26];      /* 0x748 */
+	u32     daisy[104];     /* 0x7b0..94c */
+};
+
 struct wdog_regs {
 	u16	wcr;	/* Control */
 	u16	wsr;	/* Service */