diff options
author | Eric Nelson <eric.nelson@boundarydevices.com> | 2012-09-21 11:41:42 +0000 |
---|---|---|
committer | Tom Rini <trini@ti.com> | 2012-10-15 11:54:09 -0700 |
commit | a83e1b7b8c3daa5dc82c994525ff3bf4e3bc56a3 (patch) | |
tree | f62956ff7c6a93624f1ceef03291a049032f72a2 /arch/arm/include/asm/arch-mx6/imx-regs.h | |
parent | 344da71a2089a1523ed0690d8a7b089b9f278634 (diff) |
i.MX6: define IOMUX_GPR3 register bitfields
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Diffstat (limited to 'arch/arm/include/asm/arch-mx6/imx-regs.h')
-rw-r--r-- | arch/arm/include/asm/arch-mx6/imx-regs.h | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 8834c59dcce..f9b08325eb4 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -200,6 +200,54 @@ struct src { u32 gpr10; }; +/* GPR3 bitfields */ +#define IOMUXC_GPR3_GPU_DBG_OFFSET 29 +#define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET) +#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET 28 +#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET) +#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET 27 +#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET) +#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET 26 +#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET) +#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET 25 +#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET) +#define IOMUXC_GPR3_OCRAM_CTL_OFFSET 21 +#define IOMUXC_GPR3_OCRAM_CTL_MASK (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET) +#define IOMUXC_GPR3_OCRAM_STATUS_OFFSET 17 +#define IOMUXC_GPR3_OCRAM_STATUS_MASK (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET) +#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET 16 +#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET) +#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET 15 +#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET) +#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET 14 +#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET) +#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET 13 +#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET) +#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET 12 +#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET) +#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET 11 +#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET) +#define IOMUXC_GPR3_IPU_DIAG_OFFSET 10 +#define IOMUXC_GPR3_IPU_DIAG_MASK (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET) + +#define IOMUXC_GPR3_MUX_SRC_IPU1_DI0 0 +#define IOMUXC_GPR3_MUX_SRC_IPU1_DI1 1 +#define IOMUXC_GPR3_MUX_SRC_IPU2_DI0 2 +#define IOMUXC_GPR3_MUX_SRC_IPU2_DI1 3 + +#define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET 8 +#define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET) + +#define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET 6 +#define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) + +#define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET 4 +#define IOMUXC_GPR3_MIPI_MUX_CTL_MASK (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET) + +#define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2 +#define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET) + + /* ECSPI registers */ struct cspi_regs { u32 rxdata; |