diff options
| author | Mingkai Hu <Mingkai.hu@freescale.com> | 2015-12-07 16:58:54 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-12-17 08:52:18 +0800 |
| commit | 0d6faf2bd0d12642e8b2c428d62c285f4ee28b9d (patch) | |
| tree | fbc4357334745cbdccb55e406e147f8d8789cec8 /arch/arm/include/asm/arch-fsl-layerscape/config.h | |
| parent | 2949ae521200ae5758ae395a364fcb4e85f899c0 (diff) | |
armv8/ls1043a: Implement workaround for PEX erratum A009929
Consecutive write transactions from core to PCI express outbound
path hangs after 25 to 30 transactions depending on core freq.
This erratum enable the mbist clock through COP register setting.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/arm/include/asm/arch-fsl-layerscape/config.h')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 6e5224ea1c9..49b113dc59b 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -166,6 +166,7 @@ #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 +#define CONFIG_SYS_FSL_ERRATUM_A009929 #else #error SoC not defined #endif |