diff options
| author | Landheer-Cieslak, Ronald <ronaldlandheercieslak@eaton.com> | 2017-10-25 13:46:53 +0000 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-11-17 10:53:45 -0500 |
| commit | 48c7f77128c9b1291931c481617691ff38334efc (patch) | |
| tree | f8e44325ac0c5de74289390054b13c01fafbc9a9 /arch/arm/include/asm/arch-am33xx | |
| parent | 3977dcd559e392b9a2f3c69e317527cbe8b6ae15 (diff) | |
Add UART base addresses for additional UARTs
UARTs 1 through 5 were missing in the code - added.
Also pick the default according to the configuration setting for the
console index.
Signed-off-by: Ronald Landheer-Cieslak <ronaldlandheercieslak@eaton.com>
Diffstat (limited to 'arch/arm/include/asm/arch-am33xx')
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/hardware.h | 14 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/hardware_am33xx.h | 5 |
2 files changed, 18 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h index 3437e6116d..c2cc849f32 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -53,7 +53,19 @@ #define DDR_CONTROL_BASE_ADDR 0x44E11404 /* UART */ -#define DEFAULT_UART_BASE UART0_BASE +#if CONFIG_CONS_INDEX == 1 +# define DEFAULT_UART_BASE UART0_BASE +#elif CONFIG_CONS_INDEX == 2 +# define DEFAULT_UART_BASE UART1_BASE +#elif CONFIG_CONS_INDEX == 3 +# define DEFAULT_UART_BASE UART2_BASE +#elif CONFIG_CONS_INDEX == 4 +# define DEFAULT_UART_BASE UART3_BASE +#elif CONFIG_CONS_INDEX == 5 +# define DEFAULT_UART_BASE UART4_BASE +#elif CONFIG_CONS_INDEX == 6 +# define DEFAULT_UART_BASE UART5_BASE +#endif /* GPMC Base address */ #define GPMC_BASE 0x50000000 diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h index fa9b84f95b..3e46283455 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h @@ -15,6 +15,11 @@ /* UART Base Address */ #define UART0_BASE 0x44E09000 +#define UART1_BASE 0x48022000 +#define UART2_BASE 0x48024000 +#define UART3_BASE 0x481A6000 +#define UART4_BASE 0x481A8000 +#define UART5_BASE 0x481AA000 /* GPIO Base address */ #define GPIO2_BASE 0x481AC000 |