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| author | David Wu <david.wu@rock-chips.com> | 2017-09-20 14:38:58 +0800 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2017-10-01 00:33:30 +0200 |
| commit | 364fc7315aa0e6e20f604bb8b369b4bdc0dd8e8a (patch) | |
| tree | 6bfd8955bddacb21b9769d900a3c7b9d061ad387 /arch/arm/dts | |
| parent | 615514c16dee4d43bd584ea326a5a56ebcb89c85 (diff) | |
rockchip: clk: Add rk3399 SARADC clock support
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Diffstat (limited to 'arch/arm/dts')
0 files changed, 0 insertions, 0 deletions