diff options
| author | Han Xu <han.xu@nxp.com> | 2022-09-29 16:03:47 -0500 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2022-10-10 18:28:00 +0800 |
| commit | 97fc905e7f7344fb9c2ca3c861348b2b110a51d6 (patch) | |
| tree | eb1acfbf901c4b055066a9b81c237cad6f91f06b /arch/arm/dts | |
| parent | aa4ebb661997ebe2db491693ee4a690adf20402c (diff) | |
LFU-409: imx8dxl: fix the i.MX8DXL ddr3l NAND DQS iomux setting
The DQS signal for NAND on i.MX8DXL ddr3l should come from USDHC1_CD_B
rather than EMMC0_CMD. The information on A1 schematic is wrong.
Signed-off-by: Han Xu <han.xu@nxp.com>
Reviewed-by: Frank Li <frank.li@nxp.com>
(cherry picked from commit 611d71fa8de07ae6a99c7d3bf809091236ceac27)
Diffstat (limited to 'arch/arm/dts')
| -rw-r--r-- | arch/arm/dts/fsl-imx8dxl-ddr3l-evk.dts | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/dts/fsl-imx8dxl-ddr3l-evk.dts b/arch/arm/dts/fsl-imx8dxl-ddr3l-evk.dts index 040e52912e..3fe19b9848 100644 --- a/arch/arm/dts/fsl-imx8dxl-ddr3l-evk.dts +++ b/arch/arm/dts/fsl-imx8dxl-ddr3l-evk.dts @@ -100,8 +100,8 @@ SC_P_EMMC0_CLK_CONN_NAND_READY_B 0x0e00004c SC_P_EMMC0_STROBE_CONN_NAND_CLE 0x0e00004c SC_P_EMMC0_RESET_B_CONN_NAND_WP_B 0x0e00004c - SC_P_EMMC0_CMD_CONN_NAND_DQS 0x0e00004c + SC_P_USDHC1_CD_B_CONN_NAND_DQS 0x0e00004c SC_P_USDHC1_RESET_B_CONN_NAND_WE_B 0x0e00004c SC_P_USDHC1_WP_CONN_NAND_ALE 0x0e00004c SC_P_USDHC1_VSELECT_CONN_NAND_RE_B 0x0e00004c |