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authorBJ DevOps Team <bjdevops@NXP1.onmicrosoft.com>2022-07-19 03:40:43 +0200
committerBJ DevOps Team <bjdevops@NXP1.onmicrosoft.com>2022-07-19 03:40:43 +0200
commit0bdc88f45a6cd36040667de59e05039204fcabea (patch)
tree6c53c8d61312bb7865c86cba4b6139c19b9667f0 /arch/arm/dts
parent93835308b055c9a1061a17d0baf194340164e02c (diff)
parentea9978ca7bdd701817419ae126019ac76522b2f9 (diff)
Merge remote-tracking branch 'origin/imx_v2022.04' into lf_v2022.04
* origin/imx_v2022.04: (11 commits) LFU-332-10: configs: imx8mm: ab2 target board config options LFU-332-9: include: configs: imx8mm ab2: board configs LFU-332-8: dts: arm: imx8mm ab2: target board support LFU-332-7: arm: mach imx8m: imx8mm ab2 target board configs LFU-332-6: board: freescale: imx8mm ab2: target board support ...
Diffstat (limited to 'arch/arm/dts')
-rw-r--r--arch/arm/dts/Makefile4
-rw-r--r--arch/arm/dts/imx8mm-ab2-u-boot.dtsi21
-rw-r--r--arch/arm/dts/imx8mm-ab2.dts12
-rw-r--r--arch/arm/dts/imx8mm-ab2.dtsi158
-rw-r--r--arch/arm/dts/imx8mm-ddr4-ab2-u-boot.dtsi21
-rw-r--r--arch/arm/dts/imx8mm-ddr4-ab2.dts12
-rw-r--r--arch/arm/dts/imx8mn-ab2-u-boot.dtsi10
-rw-r--r--arch/arm/dts/imx8mn-ab2.dts12
-rw-r--r--arch/arm/dts/imx8mn-ab2.dtsi146
-rw-r--r--arch/arm/dts/imx8mn-ddr3l-ab2-u-boot.dtsi18
-rw-r--r--arch/arm/dts/imx8mn-ddr3l-ab2.dts11
-rw-r--r--arch/arm/dts/imx8mn-ddr4-ab2-u-boot.dtsi10
-rw-r--r--arch/arm/dts/imx8mn-ddr4-ab2.dts12
13 files changed, 447 insertions, 0 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 247a731f2b..d596915747 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -964,9 +964,11 @@ dtb-$(CONFIG_ARCH_IMX8ULP) += \
dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-ddr4-evk.dtb \
+ imx8mm-ddr4-ab2.dtb \
imx8mm-ddr3l-val.dtb \
imx8mm-ddr4-val.dtb \
imx8mm-evk.dtb \
+ imx8mm-ab2.dtb \
imx8mm-icore-mx8mm-ctouch2.dtb \
imx8mm-icore-mx8mm-edimm2.2.dtb \
imx8mm-kontron-n801x-s.dtb \
@@ -981,8 +983,10 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
phycore-imx8mm.dtb \
imx8mn-ddr3l-evk.dtb \
imx8mn-ddr4-evk.dtb \
+ imx8mn-ddr4-ab2.dtb \
imx8mq-cm.dtb \
imx8mn-evk.dtb \
+ imx8mn-ab2.dtb \
imx8mn-var-som-symphony.dtb \
imx8mn-venice.dtb \
imx8mn-venice-gw7902.dtb \
diff --git a/arch/arm/dts/imx8mm-ab2-u-boot.dtsi b/arch/arm/dts/imx8mm-ab2-u-boot.dtsi
new file mode 100644
index 0000000000..c0b93bf9c1
--- /dev/null
+++ b/arch/arm/dts/imx8mm-ab2-u-boot.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include "imx8mm-evk-u-boot.dtsi"
+
+/ {
+ usbg2: usbg2 {
+ status = "disabled";
+ };
+};
+
+&fec1 {
+ phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+};
+
+&usbotg1 {
+ status = "okay";
+ extcon = <&ptn5150>;
+};
diff --git a/arch/arm/dts/imx8mm-ab2.dts b/arch/arm/dts/imx8mm-ab2.dts
new file mode 100644
index 0000000000..6d3667ef9a
--- /dev/null
+++ b/arch/arm/dts/imx8mm-ab2.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2020 NXP
+ */
+
+#include "imx8mm-evk.dts"
+#include "imx8mm-ab2.dtsi"
+
+/ {
+ model = "NXP i.MX8MM Audio board 2.0";
+ compatible = "fsl,imx8mm-ab2", "fsl,imx8mm";
+};
diff --git a/arch/arm/dts/imx8mm-ab2.dtsi b/arch/arm/dts/imx8mm-ab2.dtsi
new file mode 100644
index 0000000000..d945d27c54
--- /dev/null
+++ b/arch/arm/dts/imx8mm-ab2.dtsi
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 NXP
+ */
+
+/ {
+ /delete-node/ audio-codec;
+ /delete-node/ dsi-host;
+ /delete-node/ ir-receiver;
+ /delete-node/ rm67199_panel;
+ /delete-node/ sound-wm8524;
+
+ leds {
+ panel {
+ label = "green:panel";
+ gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ };
+ };
+
+ reg_ab2_ana_pwr: regulator-ab2-ana-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "ANA_12V0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ab2_ana_pwr>;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&buck5_reg>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_5V0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ab2_vdd_pwr_5v0>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ vin-supply = <&buck5_reg>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&fec1 {
+ mdio {
+ ethphy0: ethernet-phy@0 {
+ reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+ max-speed = <100>;
+ };
+ };
+};
+
+&i2c2 {
+ /delete-node/ adv7535@3d;
+ /delete-node/ tcpc@50;
+
+ pca6408_2: gpio@20 {
+ compatible = "ti,tca6408";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ ptn5150: tcpc@1d {
+ compatible = "nxp,ptn5150";
+ reg = <0x1d>;
+ status = "okay";
+
+ port {
+ typec1_dr_sw: endpoint {
+ remote-endpoint = <&usb1_drd_sw>;
+ };
+ };
+
+ typec1_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ power-role = "dual";
+ data-role = "dual";
+ try-power-role = "sink";
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+ PDO_VAR(5000, 20000, 3000)>;
+ op-sink-microwatt = <15000000>;
+ self-powered;
+ };
+ };
+};
+
+&iomuxc {
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
+ MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* ENET_PHY_RST_B */
+ MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* ENET_PHY_INT_B */
+ >;
+ };
+
+ pinctrl_ab2_ana_pwr: ab2anapwrgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41
+ >;
+ };
+
+ pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
+ >;
+ };
+};
+
+&lcdif {
+ status = "disabled";
+};
+
+&mipi_dsi {
+ status = "disabled";
+
+ /delete-node/ port@1;
+ /delete-node/ port@2;
+};
+
+&sai3 {
+ status = "disabled";
+};
+
+&usbotg1 {
+ extcon = <&ptn5150>;
+};
+
+&usdhc2 {
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+};
diff --git a/arch/arm/dts/imx8mm-ddr4-ab2-u-boot.dtsi b/arch/arm/dts/imx8mm-ddr4-ab2-u-boot.dtsi
new file mode 100644
index 0000000000..27daf58a22
--- /dev/null
+++ b/arch/arm/dts/imx8mm-ddr4-ab2-u-boot.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include "imx8mm-ddr4-evk-u-boot.dtsi"
+
+/ {
+ usbg2: usbg2 {
+ status = "disabled";
+ };
+};
+
+&fec1 {
+ phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+};
+
+&usbotg1 {
+ status = "okay";
+ extcon = <&ptn5150>;
+};
diff --git a/arch/arm/dts/imx8mm-ddr4-ab2.dts b/arch/arm/dts/imx8mm-ddr4-ab2.dts
new file mode 100644
index 0000000000..418db5789e
--- /dev/null
+++ b/arch/arm/dts/imx8mm-ddr4-ab2.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2020 NXP
+ */
+
+#include "imx8mm-ddr4-evk.dts"
+#include "imx8mm-ab2.dtsi"
+
+/ {
+ model = "NXP i.MX8MM DDR4 Audio board 2.0";
+ compatible = "fsl,imx8mm-ab2", "fsl,imx8mm";
+};
diff --git a/arch/arm/dts/imx8mn-ab2-u-boot.dtsi b/arch/arm/dts/imx8mn-ab2-u-boot.dtsi
new file mode 100644
index 0000000000..689f6f3218
--- /dev/null
+++ b/arch/arm/dts/imx8mn-ab2-u-boot.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include "imx8mn-evk-u-boot.dtsi"
+
+&fec1 {
+ phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+};
diff --git a/arch/arm/dts/imx8mn-ab2.dts b/arch/arm/dts/imx8mn-ab2.dts
new file mode 100644
index 0000000000..9a5b5f63f8
--- /dev/null
+++ b/arch/arm/dts/imx8mn-ab2.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include "imx8mn-evk.dts"
+#include "imx8mn-ab2.dtsi"
+
+/ {
+ model = "NXP i.MX8MNano LPDDR4 Audio board 2.0";
+ compatible = "fsl,imx8mn-ab2", "fsl,imx8mn";
+};
diff --git a/arch/arm/dts/imx8mn-ab2.dtsi b/arch/arm/dts/imx8mn-ab2.dtsi
new file mode 100644
index 0000000000..039f3d549a
--- /dev/null
+++ b/arch/arm/dts/imx8mn-ab2.dtsi
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+/ {
+ /delete-node/ dsi-host;
+ /delete-node/ ir-receiver;
+ /delete-node/ rm67199_panel;
+
+ gpio-leds {
+ panel {
+ label = "green:panel";
+ gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ };
+ };
+
+ reg_ab2_ana_pwr: regulator-ab2-ana-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "ANA_12V0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ab2_ana_pwr>;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_5V0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ regulator-boot-on;
+ enable-active-high;
+ };
+};
+
+&fec1 {
+ phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+
+ mdio {
+ ethphy0: ethernet-phy@0 {
+ max-speed = <100>;
+ };
+ };
+};
+
+&i2c2 {
+ /delete-node/ adv7535@3d;
+ /delete-node/ tcpc@50;
+
+ pca6408_2: gpio@20 {
+ compatible = "ti,tca6408";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ ptn5150: tcpc@1d {
+ compatible = "nxp,ptn5150";
+ reg = <0x1d>;
+ status = "okay";
+
+ port {
+ typec1_dr_sw: endpoint {
+ remote-endpoint = <&usb1_drd_sw>;
+ };
+ };
+
+ typec1_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ power-role = "dual";
+ data-role = "dual";
+ try-power-role = "sink";
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+ PDO_VAR(5000, 20000, 3000)>;
+ op-sink-microwatt = <15000000>;
+ self-powered;
+ };
+ };
+};
+
+&iomuxc {
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
+ MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x16
+ >;
+ };
+
+ pinctrl_ab2_ana_pwr: ab2anapwrgrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41
+ >;
+ };
+
+ pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
+ >;
+ };
+};
+
+&lcdif {
+ status = "disabled";
+};
+
+&mipi_dsi {
+ status = "disabled";
+
+ /delete-node/ port@1;
+ /delete-node/ port@2;
+};
+
+&usdhc2 {
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+};
+
+&usbotg1 {
+ extcon = <&ptn5150>;
+};
diff --git a/arch/arm/dts/imx8mn-ddr3l-ab2-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr3l-ab2-u-boot.dtsi
new file mode 100644
index 0000000000..9d595da3a9
--- /dev/null
+++ b/arch/arm/dts/imx8mn-ddr3l-ab2-u-boot.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include "imx8mn-ab2-u-boot.dtsi"
+
+&blob_1 {
+ filename = "ddr3_imem_1d_201810.bin";
+};
+
+&blob_2 {
+ filename = "ddr3_dmem_1d_201810.bin";
+};
+
+/delete-node/ &blob_3;
+
+/delete-node/ &blob_4;
diff --git a/arch/arm/dts/imx8mn-ddr3l-ab2.dts b/arch/arm/dts/imx8mn-ddr3l-ab2.dts
new file mode 100644
index 0000000000..b89e1ce81b
--- /dev/null
+++ b/arch/arm/dts/imx8mn-ddr3l-ab2.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
+ /*
+ * Copyright 2021 NXP
+ */
+
+#include "imx8mn-ddr3l-evk.dts"
+#include "imx8mn-ab2.dtsi"
+
+/ {
+ model = "NXP i.MX8MNano DDR3L Audio board 2.0";
+};
diff --git a/arch/arm/dts/imx8mn-ddr4-ab2-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-ab2-u-boot.dtsi
new file mode 100644
index 0000000000..6df56985d6
--- /dev/null
+++ b/arch/arm/dts/imx8mn-ddr4-ab2-u-boot.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include "imx8mn-ddr4-evk-u-boot.dtsi"
+
+&fec1 {
+ phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+};
diff --git a/arch/arm/dts/imx8mn-ddr4-ab2.dts b/arch/arm/dts/imx8mn-ddr4-ab2.dts
new file mode 100644
index 0000000000..40c9c56bfc
--- /dev/null
+++ b/arch/arm/dts/imx8mn-ddr4-ab2.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2020 NXP
+ */
+
+#include "imx8mn-ddr4-evk.dts"
+#include "imx8mn-ab2.dtsi"
+
+/ {
+ model = "NXP i.MX8MNano DDR4 Audio board 2.0";
+ compatible = "fsl,imx8mn-ab2", "fsl,imx8mn";
+};
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-23 03:12:05 +0000