diff options
| author | Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> | 2022-05-10 16:33:01 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2022-05-18 13:17:18 +0200 |
| commit | 6e38e2ea795e7e36abe8755f536747b76a29094f (patch) | |
| tree | 64a4516fcfc67dd4783464566d21c76933ac64ab /arch/arm/dts/zynqmp-zcu104-revC.dts | |
| parent | 10c29fa1cc77bc4dbf620fa5a212ae78a1cb0a73 (diff) | |
arm64: zynqmp: Set qspi tx-buswidth to 4
In all the ZynqMP boards dts files tx-buswidth is by default set to 1. Due
to this the framework only issues 1-1-1 write commands to the GQSPI driver.
But the GQSPI controller is capable of handling 1-4-4 write commands, so
updated the tx-buswidth to 4 in ZynqMP boards dts files. This would enable
the spi-nor framework to issue 1-4-4 write commands instead of 1-1-1. This
will increase the tx data transfer rate, as now the tx data will be
transferred on four lines instead on single line.
Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ad61199f55e5e00f29de6206d9d1872a52a7657e.1652193179.git.michal.simek@amd.com
Diffstat (limited to 'arch/arm/dts/zynqmp-zcu104-revC.dts')
| -rw-r--r-- | arch/arm/dts/zynqmp-zcu104-revC.dts | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index 45191569c1..752a9e38f3 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -446,7 +446,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ |