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authorMichal Simek <michal.simek@xilinx.com>2015-07-22 11:26:08 +0200
committerMichal Simek <michal.simek@xilinx.com>2015-07-28 11:56:26 +0200
commitd50cb3d64bba648998e65adf224d286d090fa43f (patch)
tree402e87bd702cb9015cad1d1f306f3c7c447fdb9a /arch/arm/dts/zynq-7000.dtsi
parentb4e9eaf71f715358afd6b9e9512e8e463f553053 (diff)
ARM: zynq: DT: Add missing interrupt for L2 pl310
Add pl310 interrupt to the Zynq devicetree. Signed-off-by: Alex Wilson <alex.david.wilson@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/dts/zynq-7000.dtsi')
-rw-r--r--arch/arm/dts/zynq-7000.dtsi1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 095c0f67e1..0b62cb0936 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -135,6 +135,7 @@
L2: cache-controller@f8f02000 {
compatible = "arm,pl310-cache";
reg = <0xF8F02000 0x1000>;
+ interrupts = <0 2 4>;
arm,data-latency = <3 2 2>;
arm,tag-latency = <2 2 2>;
cache-unified;