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authorMasahiro Yamada <yamada.masahiro@socionext.com>2015-12-16 10:54:08 +0900
committerMasahiro Yamada <yamada.masahiro@socionext.com>2015-12-23 00:08:34 +0900
commit4e1f81d4eb5ae71f7ae7aa53aad5f3d5d5b5f89b (patch)
tree531efec1b9dd223f1cbde1e7b8a675d6beb1e1ac /arch/arm/dts/uniphier-ph1-sld8.dtsi
parent8f06243aa0448d1d182cbc768845f3a642ce6731 (diff)
ARM: dts: uniphier: add outer cache nodes
These nodes are not parsed by U-Boot for now, but syncing device trees with Linux is helpful for easier diffing. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/dts/uniphier-ph1-sld8.dtsi')
-rw-r--r--arch/arm/dts/uniphier-ph1-sld8.dtsi12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi
index bafe343b784..cb28bc45082 100644
--- a/arch/arm/dts/uniphier-ph1-sld8.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi
@@ -19,6 +19,7 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
+ next-level-cache = <&l2>;
};
};
@@ -44,6 +45,17 @@
};
&soc {
+ l2: l2-cache@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
+ interrupts = <0 174 4>, <0 175 4>;
+ cache-unified;
+ cache-size = <(256 * 1024)>;
+ cache-sets = <256>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ };
+
i2c0: i2c@58400000 {
compatible = "socionext,uniphier-i2c";
status = "disabled";