diff options
| author | Samuel Holland <samuel@sholland.org> | 2022-04-27 15:31:25 -0500 |
|---|---|---|
| committer | Andre Przywara <andre.przywara@arm.com> | 2022-05-23 00:37:51 +0100 |
| commit | 6f97e028ef8064ab6ecdfb6e18e7d53bd7e44272 (patch) | |
| tree | 75b7f895de875c92359fe92051d75bb133cd2d4c /arch/arm/dts/sun9i-a80-optimus.dts | |
| parent | 70f24fa02b52b988b852c25b9ded9e86a0ef227a (diff) | |
ARM: dts: sun9i: Sync from Linux v5.18-rc1
Copy the devicetree source for the A80 SoC and all existing boards
verbatim from the Linux v5.18-rc1 tag.
This update should not impact any existing U-Boot functionality.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Diffstat (limited to 'arch/arm/dts/sun9i-a80-optimus.dts')
| -rw-r--r-- | arch/arm/dts/sun9i-a80-optimus.dts | 50 |
1 files changed, 45 insertions, 5 deletions
diff --git a/arch/arm/dts/sun9i-a80-optimus.dts b/arch/arm/dts/sun9i-a80-optimus.dts index 58a199b0e4..5c3580d712 100644 --- a/arch/arm/dts/sun9i-a80-optimus.dts +++ b/arch/arm/dts/sun9i-a80-optimus.dts @@ -82,7 +82,7 @@ reg_usb1_vbus: usb1-vbus { compatible = "regulator-fixed"; - pinctrl-names = "default"; + regulator-name = "usb1-vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; @@ -91,7 +91,7 @@ reg_usb3_vbus: usb3-vbus { compatible = "regulator-fixed"; - pinctrl-names = "default"; + regulator-name = "usb3-vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; @@ -120,6 +120,21 @@ status = "okay"; }; +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_rgmii_pins>; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + phy-supply = <®_cldo1>; + status = "okay"; +}; + +&mdio { + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; @@ -172,10 +187,26 @@ clocks = <&ac100_rtc 0>; }; +&pio { + vcc-pa-supply = <®_ldo_io1>; + vcc-pb-supply = <®_aldo2>; + vcc-pc-supply = <®_dcdc1>; + vcc-pd-supply = <®_dcdc1>; + vcc-pe-supply = <®_eldo2>; + vcc-pf-supply = <®_dcdc1>; + vcc-pg-supply = <®_ldo_io0>; + vcc-ph-supply = <®_dcdc1>; +}; + &r_ir { status = "okay"; }; +&r_pio { + vcc-pl-supply = <®_dldo2>; + vcc-pm-supply = <®_eldo3>; +}; + &r_rsb { status = "okay"; @@ -213,6 +244,10 @@ regulator-name = "vdd-cpus-09-usbh"; }; + dc1sw { + /* unused */ + }; + reg_dcdc1: dcdc1 { regulator-always-on; regulator-min-microvolt = <3000000>; @@ -260,7 +295,6 @@ }; reg_dldo2: dldo2 { - regulator-always-on; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-name = "vcc-pl"; @@ -279,14 +313,12 @@ }; reg_eldo3: eldo3 { - regulator-always-on; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-name = "vcc-pm-codec-io1"; }; reg_ldo_io0: ldo_io0 { - regulator-always-on; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-name = "vcc-pg"; @@ -374,6 +406,14 @@ */ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + /* + * The PHY requires 20ms after all voltages + * are applied until core logic is ready and + * 30ms after the reset pin is de-asserted. + * Set a 100ms delay to account for PMIC + * ramp time and board traces. + */ + regulator-enable-ramp-delay = <100000>; regulator-name = "vcc-gmac-phy"; }; |