diff options
| author | Patrick Delaunay <patrick.delaunay@foss.st.com> | 2022-09-21 09:37:13 +0200 |
|---|---|---|
| committer | Patrice Chotard <patrice.chotard@foss.st.com> | 2022-09-23 14:35:45 +0200 |
| commit | 9f7c58dc0deacd6c453ac628953741f1a6a68126 (patch) | |
| tree | 893e659f70e6061811312a32a27536010fa65d1d /arch/arm/dts/stm32mp15-ddr.dtsi | |
| parent | 86d5a06ae3b826bf7b4627e926afd5378d88c574 (diff) | |
ARM: dts: stm32mp15: update DDR node
Remove the unnecessary nodes for TFABOOT and keep the mandatory part
in SOC dtsi, only the DDRCTRL and DDRPHY addresses.
This patch allows to manage the DDR configuration setting in U-Boot
device tree only if it is needed, when CONFIG_SPL is defined.
With TFABOOT, the DDR configuration is done in TF-A BL2 and the DDR size
is dynamically computed in U-Boot since commit d72e7bbe7c28 ("ram:
stm32mp1: compute DDR size from DDRCTL registers").
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Diffstat (limited to 'arch/arm/dts/stm32mp15-ddr.dtsi')
| -rw-r--r-- | arch/arm/dts/stm32mp15-ddr.dtsi | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/dts/stm32mp15-ddr.dtsi b/arch/arm/dts/stm32mp15-ddr.dtsi index 0aac9131a6..d02f79dac6 100644 --- a/arch/arm/dts/stm32mp15-ddr.dtsi +++ b/arch/arm/dts/stm32mp15-ddr.dtsi @@ -4,7 +4,22 @@ */ #include <linux/stringify.h> +#ifdef CONFIG_SPL &ddr { + clocks = <&rcc AXIDCG>, + <&rcc DDRC1>, + <&rcc DDRC2>, + <&rcc DDRPHYC>, + <&rcc DDRCAPB>, + <&rcc DDRPHYCAPB>; + + clock-names = "axidcg", + "ddrc1", + "ddrc2", + "ddrphyc", + "ddrcapb", + "ddrphycapb"; + config-DDR_MEM_COMPATIBLE { u-boot,dm-pre-reloc; @@ -119,6 +134,7 @@ status = "okay"; }; }; +#endif #undef DDR_MEM_COMPATIBLE #undef DDR_MEM_NAME |