diff options
author | Patrice Chotard <patrice.chotard@st.com> | 2020-11-06 08:11:58 +0100 |
---|---|---|
committer | Patrick Delaunay <patrick.delaunay@st.com> | 2020-11-25 10:29:23 +0100 |
commit | 61c88ace4bad5c7956acbb952835b2fc81e99157 (patch) | |
tree | 424eb90f2993f864fbb26b655a39777d5a411f7a /arch/arm/dts/stm32f7-pinctrl.dtsi | |
parent | 63185b0a32442fe36fda3f6cb5b29d186085f179 (diff) |
ARM: dts: stm32: DT sync with kernel v5.10-rc1 for MCU's boards
Device tree alignment with kernel v5.10-rc1.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Diffstat (limited to 'arch/arm/dts/stm32f7-pinctrl.dtsi')
-rw-r--r-- | arch/arm/dts/stm32f7-pinctrl.dtsi | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/arch/arm/dts/stm32f7-pinctrl.dtsi b/arch/arm/dts/stm32f7-pinctrl.dtsi index 9314128df1..fe4cfda72a 100644 --- a/arch/arm/dts/stm32f7-pinctrl.dtsi +++ b/arch/arm/dts/stm32f7-pinctrl.dtsi @@ -127,7 +127,7 @@ st,bank-name = "GPIOK"; }; - cec_pins_a: cec@0 { + cec_pins_a: cec-0 { pins { pinmux = <STM32_PINMUX('A', 15, AF4)>; /* HDMI CEC */ slew-rate = <0>; @@ -136,7 +136,7 @@ }; }; - usart1_pins_a: usart1@0 { + usart1_pins_a: usart1-0 { pins1 { pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */ bias-disable; @@ -149,7 +149,7 @@ }; }; - usart1_pins_b: usart1@1 { + usart1_pins_b: usart1-1 { pins1 { pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */ bias-disable; @@ -162,7 +162,7 @@ }; }; - i2c1_pins_b: i2c1@0 { + i2c1_pins_b: i2c1-0 { pins { pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */ <STM32_PINMUX('B', 8, AF4)>; /* I2C1 SCL */ @@ -172,7 +172,7 @@ }; }; - usbotg_hs_pins_a: usbotg-hs@0 { + usbotg_hs_pins_a: usbotg-hs-0 { pins { pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */ <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */ @@ -192,7 +192,7 @@ }; }; - usbotg_hs_pins_b: usbotg-hs@1 { + usbotg_hs_pins_b: usbotg-hs-1 { pins { pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */ <STM32_PINMUX('C', 2, AF10)>, /* OTG_HS_ULPI_DIR */ @@ -212,7 +212,7 @@ }; }; - usbotg_fs_pins_a: usbotg-fs@0 { + usbotg_fs_pins_a: usbotg-fs-0 { pins { pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */ <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */ @@ -223,7 +223,7 @@ }; }; - sdio_pins_a: sdio_pins_a@0 { + sdio_pins_a: sdio-pins-a-0 { pins { pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */ @@ -236,7 +236,7 @@ }; }; - sdio_pins_od_a: sdio_pins_od_a@0 { + sdio_pins_od_a: sdio-pins-od-a-0 { pins1 { pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */ @@ -254,7 +254,7 @@ }; }; - sdio_pins_b: sdio_pins_b@0 { + sdio_pins_b: sdio-pins-b-0 { pins { pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */ <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */ @@ -267,7 +267,7 @@ }; }; - sdio_pins_od_b: sdio_pins_od_b@0 { + sdio_pins_od_b: sdio-pins-od-b-0 { pins1 { pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */ <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */ |