diff options
author | Marek Vasut <marex@denx.de> | 2015-06-21 17:28:53 +0200 |
---|---|---|
committer | Marek Vasut <marex@denx.de> | 2015-09-04 11:54:21 +0200 |
commit | 952caa289ee10c7426d28e37bb3130e95a6d6431 (patch) | |
tree | 03e38e7cbe8c19b0acd9b1b9a12936ed1036fa4d /arch/arm/dts/socfpga_cyclone5_sockit.dts | |
parent | a665b051b5a191c2b5c1c8ed238ccf7d29b7109b (diff) |
arm: socfpga: Add support for Terasic SoCkit board
Add support for Terasic SoCkit, which is CycloneV based board.
The board can boot either from SD/MMC or QSPI. Ethernet is also
supported.
Signed-off-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'arch/arm/dts/socfpga_cyclone5_sockit.dts')
-rw-r--r-- | arch/arm/dts/socfpga_cyclone5_sockit.dts | 92 |
1 files changed, 92 insertions, 0 deletions
diff --git a/arch/arm/dts/socfpga_cyclone5_sockit.dts b/arch/arm/dts/socfpga_cyclone5_sockit.dts new file mode 100644 index 00000000000..d7c41c83533 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_sockit.dts @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "Terasic SoCkit"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + aliases { + ethernet0 = &gmac1; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + soc { + u-boot,dm-pre-reloc; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txen-skew-ps = <0>; + txc-skew-ps = <2600>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <2000>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rtc: rtc@68 { + compatible = "stm,m41t82"; + reg = <0x68>; + }; +}; + +&mmc0 { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&qspi { + status = "okay"; + u-boot,dm-pre-reloc; + + flash0: n25q00@0 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00", "spi-flash"; + reg = <0>; /* chip select */ + spi-max-frequency = <50000000>; + m25p,fast-read; + page-size = <256>; + block-size = <16>; /* 2^16, 64KB */ + read-delay = <4>; /* delay value in read data capture register */ + tshsl-ns = <50>; + tsd2d-ns = <50>; + tchsh-ns = <4>; + tslch-ns = <4>; + }; +}; |